我正在使用Xilinx ISE,并使用CORE Generator和Architecture Wizard生成了内存。
问题在于它创建了一个写使能信号(wea)作为STD_LOGIC_VECTOR(0到0),并导致类型不匹配:
第###行:encnt附近类型错误;当前类型为std_logic; 预期的类型std_logic_vector
如何将encntstd_logic转换为一点std_logic_vector?
(ISE不允许我从内存文件中更改Wea。)
--
-- VHDL Architecture di_lib.ShiftRegister1.ShiftRegister1
--
-- Created:
-- by - 294162.UNKNOWN (VD1210)
-- at - 14:19:36 10-04-2015
--
-- using Mentor Graphics HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY WORK;
USE WORK.CALC_PKG.ALL;
LIBRARY di_lib;
USE di_lib.calc_pkg.all;
USE ieee.NUMERIC_STD.all;
ENTITY ShiftRegister1 IS
PORT(
d_out : OUT Std_Logic_Vector (7 DOWNTO 0);
multiplexer : IN Std_Logic_Vector (7 DOWNTO 0);
carry : IN std_logic;
load_out : IN std_logic;
f_code : IN std_logic_vector (2 DOWNTO 0);
out_loaded : OUT std_logic …Run Code Online (Sandbox Code Playgroud) 在我的代码中,我想在抽象类中创建一个方法,它返回一些Observable.然后,这个抽象类的实现将返回某个(指定)类型的Observable.不幸的是,Android Studio将在实现方法()中返回错误"类型不匹配":
我的MockDrawerList.getList()回报Observable<DrawerItemEntity>
请专注于execute()和buildUseCaseObservable
public abstract class UseCase(threadExecutor: ThreadExecutor,
postExecutionThread: PostExecutionThread) {
private val threadExecutor: ThreadExecutor
private val postExecutionThread: PostExecutionThread
private var subscription: Subscription = Subscriptions.empty()
init {
this.postExecutionThread = postExecutionThread
this.threadExecutor = threadExecutor
}
protected abstract fun buildUseCaseObservable(): Observable<Any>
public fun execute(useCaseSubsriber: Subscriber<Any>) {
subscription = buildUseCaseObservable()
.subscribeOn(Schedulers.from(threadExecutor))
.observeOn(postExecutionThread.getScheduler())
.subscribe(useCaseSubsriber)
}
public fun unsubsribe() {
if (!subscription.isUnsubscribed())
subscription.unsubscribe()
}
}
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Inject
class GetDrawerListUseCase(threadExecutor: ThreadExecutor,
postExecutionThread:PostExecutionThread) : UseCase(threadExecutor, …Run Code Online (Sandbox Code Playgroud) 我期待在verilog HDL中实现32位并行并行输出.这是我写的代码......
module pipo(input_seq, answer,reset, clock);
input [31:0] input_seq;
input reset,clock;
output [31:0] answer;
always @ (reset)
begin
if(!reset)
begin
answer[31:0]<=1'b0;
end
end
always @ (posedge clock)
begin
answer[31:1]<=input_seq[30:0];
end
endmodule
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但是,这会导致以下错误日志(使用iverilog):
pipo.v:10: error: answer['sd31:'sd0] is not a valid l-value in pipo.
pipo.v:4: : answer['sd31:'sd0] is declared here as wire.
pipo.v:16: error: answer['sd31:'sd1] is not a valid l-value in pipo.
pipo.v:4: : answer['sd31:'sd1] is declared here as wire.
Elaboration failed
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有什么问题?