我应该如何在测试平台中创建时钟？我已经找到了一个答案,但是有关堆栈溢出的其他人已经建议有其他或更好的方法来实现这一点:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_tb IS
END test_tb;
ARCHITECTURE behavior OF test_tb IS
COMPONENT test
PORT(clk : IN std_logic;)
END COMPONENT;
signal clk : std_logic := '0';
constant clk_period : time := 1 ns;
BEGIN
uut: test PORT MAP (clk => clk);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 …我有两个2D数组:
type array1x1D is array (0 to 10) of std_logic_vector(0 to 10); -- Array of arrays
type array2D is array (0 to 10, 0 to 10) of std_logic; -- Real 2D array
如何访问std_logic_vectors前者的范围和后者的范围？我当然可以使用变量来跟踪它们的大小,但我宁愿避免这种情况.我试图使用GENERATE语句循环数组.
在VHDL中测试简单的生活游戏实现时，在打印出“测试结束”消息后，空测试台的GHDL模拟会挂起，CPU使用率达到100％。
这是代码：
----- Package ------------------------------
library ieee;
use ieee.std_logic_1164.all;
package data_types is
type array2D is array (0 to 10, 0 to 10) of std_logic;
end data_types;
----- Main Code ----------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.data_types.all;
entity de0 is
port (matrix : inout array2D);
end de0;
architecture life of de0 is
-- Return the integer value of a cell, treating all out of bounds as 0
function cellValue (matrix : array2D; x, y : integer) return integer is
begin
if …