如何在Chisel中初始化Bundle的Reg？

Question

我为我的特定数据声明了一个捆绑包：

class RValue (val cSize: Int = 16) extends Bundle {
  val rvalue = Output(UInt(cSize.W))
  val er     = Output(UInt((cSize/2).W))
  val part   = Output(Bool()) /* set if value is partial */
}

我想将它用作我的模块中的寄存器：

  val valueReg = Reg(new RValue(cSize))
//...
  valueReg.rvalue := 0.U
  valueReg.er := 0.U

效果很好。但我想在 Register 声明中使用 RegInit() 对其进行初始化。是否可以 ？

  val valueReg = RegInit(new RValue(cSize), ?? ) ??

Answer 1

Chick's answer of using Bundle Literals is the cool new way and is nice because you can give a Bundle arbitrary values in a single expression.

If you just want to zero-out the register at reset type, you could always cast from a literal zero to the Bundle:

val valueReg = RegInit(0.U.asTypeOf(new RValue(cSize))

You can do similar things with any literal if you want, but I wouldn't recommend it unless you're zeroing out or setting everything to 1s.

For setting each field to some other value, I think Chick's way is better, but the normal style you'll see in older code is something like:

val valueReg = RegInit({
  val bundle = Wire(new RValue(cSize))
  bundle.rvalue := 1.U
  bundle.er := 2.U
  bundle.part := 3.U
  bundle
})

In Scala, you can put { } anywhere an expression is needed and the last expression in the Block will be the return value. Thus we can create a Wire with the values we want to reset the register to and then pass that Bundle as the initialization value. It would be equivalent to write:

val valueRegInit = Wire(new RValue(cSize))
valueRegInit.rvalue := 1.U
valueRegInit.er := 2.U
valueRegInit.part := 3.U
val valueReg = RegInit(valueRegInit)

I hope this helps!