如何将 C 编译输出文件（Linux 内核模块）放在与源文件不同的目录中（使用 Makefile）

Question

我已经查看了这些以及这些其他解决方案，但无法编写正确的 Makefile 来产生我想要的结果。

所以，我有这个simple.c文件。它模拟linux内核模块的加载和删除。地点：/path/to/dir/simple.c

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>

/* This function is called when the module is loaded. */
int simple_init(void)
{
       printk(KERN_INFO "Loading Module\n");

       return 0;
}

/* This function is called when the module is removed. */
void simple_exit(void) {
    printk(KERN_INFO "Removing Module\n");
}

/* Macros for registering module entry and exit points. */
module_init( simple_init );
module_exit( simple_exit );

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Simple Module");
MODULE_AUTHOR("SGG");

我也将它Makefile放在与simple.c, location:相同的目录中/path/to/dir/Makefile。

obj-m += simple.o
all:
        make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
        make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean

在终端上运行时：

cd path/to/dir/
make

一切都被正确编译（在同一目录中path/to/dir/。

我想要的是这个：

的位置simple.c在/path/to/dir/src/。

的位置Makefile在/path/to/dir/。

输出在/path/to/dir/bin/or/and 中的位置/path/to/dir/obj/。

当make运行时，输出应到底bin，obj目录。

Makefile ( /lib/modules/$(shell uname -r)/build) 中有一些我不太明白的复杂情况。所有的各种改变Makefile为了达到预期的结果，都以错误告终。

我该怎么做？

编辑：

该Makefile中/lib/modules/$(shell uname -r)/build有如下代码：

VERSION = 4
PATCHLEVEL = 4
SUBLEVEL = 162
EXTRAVERSION =
NAME = Blurry Fish Butt

# *DOCUMENTATION*
# To see a list of typical targets execute "make help"
# More info can be located in ./README
# Comments in this file are targeted only to the developer, do not
# expect to learn how to build the kernel reading this file.

# o Do not use make's built-in rules and variables
#   (this increases performance and avoids hard-to-debug behaviour);
# o Look for make include files relative to root of kernel src
MAKEFLAGS += -rR --include-dir=$(CURDIR)

# Avoid funny character set dependencies
unexport LC_ALL
LC_COLLATE=C
LC_NUMERIC=C
export LC_COLLATE LC_NUMERIC

# Avoid interference with shell env settings
unexport GREP_OPTIONS

# We are using a recursive build, so we need to do a little thinking
# to get the ordering right.
#
# Most importantly: sub-Makefiles should only ever modify files in
# their own directory. If in some directory we have a dependency on
# a file in another dir (which doesn't happen often, but it's often
# unavoidable when linking the built-in.o targets which finally
# turn into vmlinux), we will call a sub make in that other dir, and
# after that we are sure that everything which is in that other dir
# is now up to date.
#
# The only cases where we need to modify files which have global
# effects are thus separated out and done before the recursive
# descending is started. They are now explicitly listed as the
# prepare rule.

# Beautify output
# ---------------------------------------------------------------------------
#
# Normally, we echo the whole command before executing it. By making
"/lib/modules/4.4.0-141-generic/build/Makefile" [readonly] 1650L, 57062C

Answer 1

我不知道我是否理解了这个问题。首先，我建议您在 SRC 文件夹中找到源代码。之后，选择要创建 Makefile 的目录。

下一步是定义链接程序所需的代码集。不要忘记 SRC 文件夹的路径。

现在是时候创建目标文件了。在此步骤中，选择选项 -o [path_obj]/[file_name].o。

最后一步是链接程序，不要忘记对象位于 [path_obj] 文件夹中。

一个简单的例子可以是：

#path definitions

SRC_path = /path_to_src/
OBJ_path = /path_to_obj/
BIN_path = /path_to_bin/

#lists definitions
SRC = [file1].c [file2].c
OBJ = $(addsuffix .o, $(basename ${SRC}))

#Suffixes definitions
.suffixes:
.suffixes: .c .o

#Create objects
.c.o:   gcc -I[include_files] -c $(SRC_path)$< -o $(OBJ_path)$@

#Link program
TAG:    gcc  $(addprefix $(OBJ_path), $(OBJ)) -o $(BIN_path)[program_name]

希望对你有帮助