那些遇到过的问题

VHDL(Xilinx工具链)我被"阵列修整"所打破

Wos*_*ame 1 synthesis vhdl compiler-warnings

我有一个双文件VHDL项目,我有初学者的困难.

它需要系统时钟并使用30位时钟分频器(我只使用少量非连续位)驱动原始串行端口模块(仅输出TX)模块定期吐出8位字符.

似乎在合成过程中,优化器正在删除许多基本信号,这是我没想到的.

顶级文件"Glue.vhd"......

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity Glue is
    port(
        clk : in std_logic;
        tx  : out std_logic;
        LED : out std_logic_vector(1 downto 0)
        );
end entity Glue;

architecture behavioural of Glue is
    signal divider : unsigned(29 downto 0);
begin
    LED(1) <= '0';

    ser_tx : entity SerialTX
    port map (
            baud_clk => divider(12),
            byte_to_transmit => std_ulogic_vector(divider(29 downto 22)),
            poke => divider(20),
            busy => LED(0),
            serial_out => tx
            );

    clocker : process(clk)
    begin
        IF(rising_edge(clk)) then
            divider <= divider + 1;
        END IF;
    end process clocker;
end architecture behavioural;
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SerialTX.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity SerialTX is
    port (
        baud_clk         : in  std_logic;
        byte_to_transmit : in  std_ulogic_vector(7 downto 0); --the byte that we want to transmit
        poke             : in  std_logic;                     --a rising edge causes the byte to be sent out
        busy             : out std_logic;                     --wait for this to go low before transmiting more data
        serial_out       : out std_logic                      --the RS232 serial signal
        );
end SerialTX;

architecture behavioural of SerialTX is
    signal bit_buf                : unsigned(9 downto 0); --(STOP bit) & (8 data bits) & (START bit)
    signal internal_busy          : std_logic;
    shared variable bit_counter   : integer range 0 to 10;
begin
    busy <= internal_busy;

    busy_handler : process(poke) is
    begin
        if(rising_edge(poke)) then
            internal_busy <= '1';
        end if;
        if(bit_counter = 0) then
            internal_busy <= '0';
        end if;
    end process busy_handler;

    do_transmit : process(baud_clk) is
    begin
        if(rising_edge(baud_clk)) then 
            if((internal_busy = '1') and (bit_counter = 0)) then
                bit_counter := 10;
                bit_buf <= unsigned('1' & byte_to_transmit & '0');
            end if;

            serial_out <= bit_buf(0);
            bit_buf <= bit_buf srl 1;
            bit_counter := bit_counter - 1;
        end if;
    end process do_transmit;
end behavioural;
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合成过程中的警告(没有错误提醒你)如下......

WARNING:Xst:647 - Input <byte_to_transmit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1710 - FF/Latch <bit_buf_9> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_8> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_7> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_6> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_5> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_4> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_3> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_2> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_1> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_0> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <serial_out> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2404 -  FFs/Latches <bit_buf<9:0>> (without init value) have a constant value of 0 in block <SerialTX>.
WARNING:Xst:1710 - FF/Latch <serial_out> (without init value) has a constant value of 0 in block <SerialTX>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <divider_21> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_22> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_23> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_24> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_25> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_26> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_27> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_28> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_29> of sequential type is unconnected in block <Glue>.
WARNING:Route:455 - CLK Net:divider<20> may have excessive skew because     0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:divider<12> may have excessive skew because     0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
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我已经跟踪了源代码中的连接,我找不到我正在犯的错误.我觉得我错过了一些我在作业中没有涉及的边缘/角落情况.

标记为"(没有初始值)"的项目我试图通过给它们默认值来纠正无效.标记为"未连接的块"的是令人困惑的.

我该怎么做才能满足合成器的要求？

FRo*_*Rob 5

虽然user1155120是正确的,你应该指定库或进行组件绑定,但是你的工具显然找到了正确的实体,因为这是你的逻辑优化的地方.

首先,不要使用 

use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
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一起.除了处理遗留代码之外,您应该使用numeric_std.

真正的问题是双重的:

  • 您没有初始化您的计数器变量,它不正确.
  • 您的输入数据永远不会进入并行加载移位寄存器,因此会被修整.

您希望计数器以什么价值开始？IIRC,未初始化的整数类型将采用其范围内的最低有效值.但是,最好在任何情况下都明确开头.然而,实际上FPGA中没有整数 - 只是冷硬的触发器.0到10的范围使用至少4位,因此使用4个触发器.但是,从0到"-1"将下溢并回绕到15而不是您可能期望的10. internal_busy意图是触发器,但也没有初始化.我说有意,因为它实际上是异步重置的bit_counter.这种异步重置本身是有问题的,几乎肯定不是你想要的:

busy_handler : process(poke) is -- <-- wrong sensitivity list
begin
    if(rising_edge(poke)) then
        internal_busy <= '1';
    end if;
    if(bit_counter = 0) then   -- <-- not clocked
        internal_busy <= '0';
    end if;
end process busy_handler;
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你混合了时钟和组合代码.您的模拟将关闭,因为虽然internal_busy并行将在硬件中并行,但您的模拟工具将仅显示更改的更新poke.

-- can never happen, because bit_counter = 0 means internal_busy is forced to '0'
if((internal_busy = '1') and (bit_counter = 0)) then
    bit_counter := 10;
    bit_buf <= unsigned('1' & byte_to_transmit & '0');
end if;
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如果没有这个逻辑,bit_buf确实会9'h000(Xilinx工具假设的值 - 你没有给出任何!).这是以下几行告诉您的内容:

WARNING:Xst:1710 - FF/Latch <bit_buf_9> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_8> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_7> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_6> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_5> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_4> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_3> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_2> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_1> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_0> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <serial_out> (without init value) has a constant value of 0 in block <SerialTX>. This FF/Latch will be trimmed during the optimization process.
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  1. bit_buf_9永远为零,将被硬零(逻辑或结构)取代.因此它的触发器是冗余的并且可以被修整.
  2. bit_buf_{8..0}被确定等同于其他一些触发器(这里:) bit_buf_9.然而,该触发器被修整,因此,这些触发器也将被修整.
  3. bit_buf_9饲料serial_out,所以它也被修剪.

其余的错误消息:

WARNING:Xst:647 - Input <byte_to_transmit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2677 - Node <divider_21> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_22> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_23> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_24> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_25> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_26> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_27> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_28> of sequential type is unconnected in block <Glue>.
WARNING:Xst:2677 - Node <divider_29> of sequential type is unconnected in block <Glue>.
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  1. byte_to_transmit 未使用且不是顶级块的一部分,它将不会被保留.
  2. divider(29 downto 22)连接到byte_to_transmit.由于该端口将被移除,因此最后使用的触发器之后的所有触发器divider(20)都可以被优化掉.

时钟警告:

WARNING:Route:455 - CLK Net:divider<20> may have excessive skew because     0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:divider<12> may have excessive skew because     0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
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  1. divider(20)并divider(12)用作时钟.
  2. divider(20)并且divider(12)由逻辑生成:LUT和触发器在一个或多个切片内.根据FPGA的不同,有一些可以反馈到时钟路由资源.
  3. 在您的情况下,工具没有找到在时钟路由资源上路由这些信号的方法,并且必须使用通常为逻辑信号保留的资源,因此偏差可能过大.

这些时钟错误可以通过1.使用clk两个模块的公共时钟和2.使用poke和baud_clk作为时钟启用来避免:

clk_en_p: process (clk) is
begin

if (rising_edge(clk)) then
    if (clk_en = '1') then
        my_signal <= assignment;
    end if;
end if;
end process clk_en_p;
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总而言之,你应该编写一个测试平台,并在综合之前模拟你的设计,正如Brian Drummond建议的那样.

在编写实现之前编写测试平台的各个部分通常很有帮助,因为它会强制您考虑组件的接口以及您希望它在实际编写之前的反应.

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