RISC-V 火箭缓存一致性

Question

对于RISC-V Rocket 处理器，缓存采用什么样的写策略（例如Write Back + Allocate、Write Through + No Allocate）？L1 缓存如何与 RISC-V 中的 L2 缓存保持一致？

Answer 1

RISC-V 是一种 ISA（指令集架构），而不是处理器。因此，ISA 没有提及缓存回写策略或一致性设计。这些决定由各个处理器设计团队决定。事实上，它们甚至不需要缓存。

The only thing RISC-V has to say about memory is the "memory consistency model". RISC-V uses a fairly relaxed consistency model, and thus it is possible for two RISC-V threads to see two different sequences/interleavings of memory operations (as opposed to "sequential consistency" where all threads see the same interleaving).

Edit (now that the question clarifies it is only asking about the Berkeley Rocket processor):

As of 2015 Sept 9, Rocket's L1 cache is write-back+allocate. L1's are kept coherent via snoop requests. Each Rocket core sits on a "Rocket Tile" that contains an L1.

一个可选的 L2 位于 Rocket 板块之外。火箭板块仲裁对单个 L2 的访问。L2 是包含的并保存所有 L1 数据。然而，L2 可能保存过时的数据，但如果一个核心请求该数据，L2 将知道哪个 L1 保存数据的当前副本，并会适当地发送释放请求。