在一些测试平台代码中,我使用一个过程来处理信号。然后我在不同的信号上按顺序多次使用这个程序。只要我明确定义信号,这就可以正常工作;一旦我在循环中索引信号,它就会失败
(vcom-1450) 正式“s”的实际(索引名称)不是静态信号名称。
为什么这是不可能的,我该如何解决?可能我可以将它移动到 a for ... generate,但是我想do_something以一个很好定义的顺序被调用。
library ieee;
use ieee.std_logic_1164.all;
entity test is
end test;
architecture tb of test is
signal foo : std_logic_vector(1 downto 0);
begin
dummy: process is
procedure do_something (
signal s : out std_logic
) is begin
s <= '1';
report "tic";
wait for 1 ns;
-- actually we would do something more interesting here
s <= '0';
report "toc";
end procedure;
begin
-- This works well, but requires manual loop-unrolling
do_something(foo(0));
do_something(foo(1));
-- This should do the same
for i in foo'range loop
-- This is the offending line:
do_something(foo(i));
end loop;
wait; -- for ever
end process dummy;
end architecture tb;
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我正在使用 ModelSim 10.4 PE。
有趣的是,如果foo是进程的局部变量,(并s进行调整以适应)ghdl 会编译它。这突出了原始版本中的问题。“for”循环需要一直驱动整个过程,foo因为你不能让信号驱动器随意出现或消失——它不能对它驱动的位产生矛盾(正如你所看到的,程序尝试在不同时间驱动不同的位)。
因此,如果您可以重新调整您的应用程序以允许变量更新语义,并foo为进程创建一个局部变量,那将起作用。(如果您想看到效果,您必须在每次“等待”之前将其值复制到信号中!)
或者,将整个foo信号和索引传递给子程序,以便后者始终foo按照以下方式驱动所有内容......(我还添加了丢失的位并修复了虚假的并发“等待”:将来,请检查您的代码示例在发布之前实际编译!)
library ieee;
use ieee.std_logic_1164.all;
entity test is
end test;
architecture tb of test is
signal foo : std_logic_vector(1 downto 0);
begin
dummy: process is
procedure do_something (
signal s : out std_logic_vector(1 downto 0);
constant i : in natural
) is begin
s <= (others => '0');
s(i) <= '1';
report "tic";
wait for 1 ns;
-- actually we would do something more interesting here
s(i) <= '0';
report "toc";
end procedure;
begin
-- This works well, but requires manual loop-unrolling
do_something(foo,0);
do_something(foo,1);
-- This should do the same
for i in foo'range loop
-- This is the offending line:
do_something(foo,i);
end loop;
wait; -- for ever
end process dummy;
end architecture tb;
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