Ald*_*doT 4 verilog system-verilog
在非可合成代码中,有什么区别:
@(a==1);
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和
@(posedge a);
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他们真的表现得一样吗?
以下示例(在EDA Playground上)显示它们不相同:
module test;
logic a = 1'b0;
initial begin
#100ns a <= 1'b1;
#100ns a <= 1'b0;
#100ns a <= 1'b1;
#1000ns $finish;
end
initial begin
@(a == 1'b1)
$display("%t : a == 1 (1) %b",$realtime, a);
@(a == 1'b1)
$display("%t : a == 1 (2) %b",$realtime, a);
@(a == 1'b1)
$display("%t : a == 1 (3) %b",$realtime, a);
end
initial begin
@(posedge a)
$display("%t : posedge a (1)",$realtime);
@(posedge a)
$display("%t : posedge a (2)",$realtime);
@(posedge a)
$display("%t : posedge a (3)",$realtime);
end
endmodule
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哪个显示
100 : posedge a (1)
100 : a == 1 (1) 1
200 : a == 1 (2) 0
300 : a == 1 (3) 1
300 : posedge a (2)
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@(posedge a)从x/z/0开始真正转换为1时取消阻止.
@(a == 1)在更改之前或之后的更改中为true时取消阻止.
当一个被认为是比特时它只能保持0或1,2状态而不是4状态(0,1,x,z).因此posedge只能是0 - > 1过渡.在modelsim 10.1中,它不会改变示例的行为.AldoT(OP)观察到@(a==1)现在的行为与@(a).