用于将verilog输出写入文本文件的测试平台

Question

我无法在文本文件中获得正确的输出,但是在modelsim中的模拟非常好..但是在将其写入文本文件时,每次输入都获得XX.可能有一些语法错误或其他一些.如果有任何可以帮助plz写下测试工作台来写一个触发器的dout(输出)(作为一个例子),每个dout(输出)显示在文本文件的新行中.

码:

module LFSR( clk,reset,out);
parameter width =4;
input clk,reset;
output [width-1:0] out ;
reg [width-1:0] lfsr;

integer r;
wire feedback = lfsr[width-1]^lfsr[width-2];


always @(posedge clk)
  if (reset)
    begin
      lfsr <= 4'b1000; 
    end
  else
    begin
      lfsr[0] <= feedback;
      for(r=1;r<width;r=r+1)
        lfsr[r]<=lfsr[r-1];
    end

  assign out=lfsr;
endmodule

试验台:

module aaatest();

  parameter width =4;
  reg clk,reset;
  wire [width-1:0] out;
  reg [width-1:0] lfsr[13:0];
  integer f,i;

  initial
    begin
      f = $fopen("output.txt","w");
    end

    LFSR patt (clk,reset,out);

    always #5 clk=~clk;

    initial begin
      clk=1; reset=1;
      #10 reset=0;
      # 140 $stop;
    end

    initial
      begin
        clk=1;
        for (i = 0; i<14; i=i+1)
          @(posedge clk)
            lfsr[i]<= out;
      end

    initial begin
      for (i = 0; i<14; i=i+1)
        $fwrite(f,"%b\n",lfsr[i]);
    end

    initial begin
      $display("clk out");
      $monitor("%b,%b", clk, out);
    end   

    initial
      begin
        $fclose(f);  
      end
    endmodule

Answer 1

我想请您考虑以下代码部分:

initial begin
  f = $fopen("output.txt","w");
end

initial begin
  for (i = 0; i<14; i=i+1)
    $fwrite(f,"%b\n",lfsr[i]);
end

initial begin
  $fclose(f);  
end

在描述硬件时,我们进行了大规模并行仿真.所有首字母都是在同一时间开始,时间为0.

如果这样可以工作,因为无法保证在写入文件之前打开文件,所以在重置模拟逻辑之前,您将在零时写入文件.

下面的内容可能更合适:

initial begin
  f = $fopen("output.txt","w");

  @(negedge reset); //Wait for reset to be released
  @(posedge clk);   //Wait for fisrt clock out of reset

  for (i = 0; i<14; i=i+1) begin
    $fwrite(f,"%b\n",lfsr[i]);
  end

  $fclose(f);  
end

为了跟进Gregs建议过早发布重置,请考虑类似于:

initial begin
  clk=0; reset=1; //Clock low at time zero
  @(posedge clk);
  @(posedge clk);
  reset=0;
  # 140 $stop;
end

其中2个时钟上升沿保持复位.

用工作示例更新

发生了一些奇怪的事情,你之后调用$stop(Not $finish)#140但是也尝试循环14次,$ stop意味着只执行4个循环.

您的测试程序由2个initial begins并行工作而不是一个顺序执行的程序组成.您没有延迟写出您的文本文件,并且您直接编写了lfsr的缓冲版本而不是lfsr输出.

以下示例正确模拟并写入您要查找的文本文件:

module aaatest();

  parameter width =4;
  reg   clk,reset;
  wire [width-1:0] out;
  reg  [width-1:0] lfsr[13:0];
  integer f,i;

  LFSR patt (clk,reset,out);

  always #5 clk=~clk;

  //Clock and reset release
  initial begin
    clk=0; reset=1; //Clock low at time zero
    @(posedge clk);
    @(posedge clk);
    reset=0;
  end

  initial begin
    f = $fopen("output.txt","w");

    @(negedge reset); //Wait for reset to be released
    @(posedge clk);   //Wait for fisrt clock out of reset

    for (i = 0; i<14; i=i+1) begin
      @(posedge clk);
      lfsr[i] <= out;
      $display("LFSR %b", out);
      $fwrite(f,"%b\n",   out);
    end

    $fclose(f);  

    $finish;
  end
endmodule