VHDL LUT 模块的设计

Question

描述：我正在尝试将 vhdl 模块编写为具有 4 个输入和 3 个输出的 LUT（查找表）。我希望我的 3 位输出是一个二进制数，等于输入中 1 的数量。

我的真值表：

ABCD|XYZ
0000|000
0001|001
0010|001
0011|010
0100|011 0101|010
0110|010 0111| 011 1000|001 1001 |010 1010
|010 1011|011 1100|010 1 101|011 1110|011 1111| 100

我的VHDL代码：

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity lut is
Port (
a : in STD_LOGIC; 
b : in STD_LOGIC; 
c : in STD_LOGIC; 
d : in STD_LOGIC; 
x : out STD_LOGIC; 
y : out STD_LOGIC; 
z : out STD_LOGIC);  

end lut;   

architecture Behavioral of lut is  
signal s0: STD_LOGIC;
signal s1: STD_LOGIC;
signal s2: STD_LOGIC;  
signal s3: STD_LOGIC;
signal s4: STD_LOGIC;
signal s5: STD_LOGIC;
signal s6: STD_LOGIC;
signal s7: STD_LOGIC; 
signal s8: STD_LOGIC;
signal s9: STD_LOGIC;
signal s10: STD_LOGIC;
signal s11: STD_LOGIC;
signal s12: STD_LOGIC;
signal s13: STD_LOGIC;

begin 
----------MUX1----------- 
process(a,b) 
begin
if a='0' 
then s0<=a;
else
s0<=b;
end if; 
end process; 

--------MUX2---------- 
process(a,b) 
begin
if a='0' 
then s1<=a;
else
s1<=b; 
end if;
end process;

---------MUX3-----------
process(a,b) 
begin
if a='0' 
then s2<=a;
else
s2<=b;
end if; 
end process;
---------MUX4-----------
process(a,b) 
begin
if a='0' 
then s3<=a;
else
s3<=b;
end if; 
end process;
---------MUX5-----------
process(c,d,a) 
begin
if a='0' 
then s4<=c;
else
s4<=d;
end if; 
end process;
---------MUX6-----------
process(c,d,a) 
begin
if a='0' 
then s5<=c;
else
s5<=d;
end if; 
end process;
---------MUX7-----------
process(c,d,a) 
begin
if a='0' 
then s6<=c;
else
s6<=d;
end if; 
end process;
---------MUX8-----------
process(c,d,a) 
begin
if a='0' 
then s7<=c;
else
s7<=d;
end if; 
end process;
---------MUX9-----------
process(s0,s1,b) 
begin
if b='0' 
then s8<=s0;
else
s8<=s1;
end if; 
end process;
---------MUX10-----------
process(s2,s3,b) 
begin
if b='0' 
then s9<=s2;
else
s9<=s3;
end if; 
end process;
---------MUX11-----------
process(s4,s5,b) 
begin
if b='0' 
then s10<=s4;
else
s10<=s5;
end if; 
end process;
---------MUX12-----------
process(s6,s7,b) 
begin
if b='0' 
then s11<=s6;
else
s11<=s7;
end if; 
end process;
---------MUX13-----------
process(s8,s9,c) 
begin
if c='0' 
then s12<=s8;
x<= s8;
else
s12<=s9;
x<= s9;
end if; 
end process;
---------MUX14-----------
process(s10,s11,c) 
begin
if c='0' 
then s13<=s10;
z<=s10;
else
s13<=s11; 
z<=s11
end if; 
end process; 
---------MUX15-----------
process(s12,s13,d) 
begin
if d='0' 
then y<=s12;
else
y<=s13;
end if; 
end process;
end Behavioral;

假设：我总共需要 15 个多路复用器来模拟我的需求。它们将级联到一个输出。我总共有 15 个进程，如上所示。

问题：
1.) 我为多路复用器 ABCD 选择什么？
2.) 我是否以正确的方式建模？我能从所提供的信息中实现我想要的目标吗？
3.）如果有更好的方法或者您有不同的想法，您能提供一个例子吗？
4.）我没有得到我的 xyz 输出，它很接近，但我做错了什么？

我试图提供尽可能多的研究。如果您有任何疑问我会立即回复

Answer 1

除非你只是为了好玩或学习而在VHDL中闲逛，如果你想要LUT，就直接写成LUT。可能没有理由将其分解为低级门和多路复用器。相反，只需描述您想要的行为，然后让 VHDL 为您完成工作：

例如，下面是您所描述的组合逻辑 LUT 的简单 VHDL：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Number_of_Ones is
    port (
        --- mapped 3=a, 2=b, 1=c, 0=d
        abcd : in std_ulogic_vector(3 downto 0);
        -- mapped x=2, y=1, z=0
        xyz  : out std_ulogic_vector(2 downto 0);
    );
end entity;

architecture any of Number_of_Ones is
begin

    process (abcd) is
    begin
        case abcd is      
        --abcd|xyz
        when "0000" => xyz <= "000";
        when "0001" => xyz <= "001";
        when "0010" => xyz <= "001";
        when "0011" => xyz <= "010";
        when "0100" => xyz <= "011";
        when "0101" => xyz <= "010";
        when "0110" => xyz <= "010";
        when "0111" => xyz <= "011";
        when "1000" => xyz <= "001";
        when "1001" => xyz <= "010";
        when "1010" => xyz <= "010";
        when "1011" => xyz <= "011";
        when "1100" => xyz <= "010";
        when "1101" => xyz <= "011";
        when "1110" => xyz <= "011";
        when "1111" => xyz <= "100";
        end case;
    end process;
end architecture; 

As you can see, this is exactly your truth table copied in and just modified to fit VHDL syntax. You can of course write this in several different ways and you might wish to map ports differently, etc, but this should get you on the right track.