小编Kat*_*pio的帖子

对于一个类,我被要求编写一个VHDL过程,它接受两个整数输入A和B,并用A代替A + B和B. 我编写了以下程序和testbench.它完成了实现和行为语法检查,但它不会模拟.虽然我没有错误,但我确实收到一些警告,说明A和B处于组合反馈循环中.有人可以解释问题可能是什么吗？

模块:

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

 entity Problem2 is
Port ( A : inout  integer;
       B : inout  integer);
 end Problem2;

 architecture Behavioral of Problem2 is

procedure AB (signal A,B: inout integer) is 
begin
A<=A+B after 20 ns;
B<=A-B after 30 ns;
end AB;

begin

AB(A=>A, B=>B);

end Behavioral;

试验台:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Problem2_test IS
END Problem2_test;

ARCHITECTURE behavior OF Problem2_test IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Problem2
    PORT(
     A …