当我尝试写入a [b + 1]时,其中b的所有位均为'1'时,reg a [0]的值不会更新,但是当我尝试a [b + 1'b1]时,它会更新更新
awaddr_wa <= awaddr_wa + 2;
awaddr[awaddr_wa] <= AWADDR_M;
awlen [awaddr_wa] <= 4'd0;
awaddr[awaddr_wa+6'd1] <= AWADDR_M+16;
awlen [awaddr_wa+6'd1] <= 4'd0
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所以为什么?
verilog ×1