首先看一下设计右移寄存器的三个代码示例,它允许用户在算术右移或逻辑右移之间进行选择:
例1:
module shiftr (data, shamt, arith, result);
input [8 - 1:0] data;
input [3 - 1:0] shamt;
input arith;
output [8 - 1:0] result;
wire [8 - 1:0] arith_shift;
assign arith_shift = $signed(data) >>> shamt;
assign result = arith ? arith_shift : (data >> shamt);
endmodule
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例2:
module shiftr (data, shamt, arith, result);
input [8 - 1:0] data;
input [3 - 1:0] shamt;
input arith;
output [8 - 1:0] result;
assign result = arith ? (($signed(data)) >>> shamt) : …Run Code Online (Sandbox Code Playgroud) verilog ×1