小编sam*_*sam的帖子

我正在研究一个项目,但无论我做什么,我都无法理解这段代码的作用.由于我不熟悉VHDL,因此我很难理解这段代码的用途.

library iee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.my_package.all;

Entity multiplier is

    generic (size: integer :=4);
    Port (a,b : in unsigned( size-1 downto 0);
        y : out unsigned( size-1 downto 0));

End multiplier ;

ARCHITECTURE behavior of multiplier is

Begin

    y<= mult(a,b);

End behavior;