小编Jim*_*Jim的帖子

我有一个非常奇怪的问题,我不是100%为什么编译器抱怨.代码如下:

variable a : std_logic_vector(2 downto 0);
variable b : std_logic;
....
if (a = "100") AND (b) then
  -- do something
elsif (a = "011") OR (b) then
  -- do something else

然后我收到错误消息:

 "AND can not have such operands in this context",
 "OR can not have such operands in this context", respectively for the second IF   

声明.

任何人都知道为什么VHDL不喜欢这种结构,如果有解决方法呢？

谢谢,吉姆