小编Ale*_*lex的帖子

模拟器中信号Q_VLD1和Q_VLD2的不同延迟原因是什么？ 模拟结果.它是否是模拟器的预期行为？

我使用Xilinx Isim.它有代码和测试平台:

entity assign_test is
    port(CLK   : in  STD_LOGIC;
         D_VLD : in  STD_LOGIC;
         Q_VLD1 : out STD_LOGIC;
         Q_VLD2 : out STD_LOGIC
    );
end assign_test;

architecture Behavioral of assign_test is
    signal D_VLD_i : std_logic;
    signal d_vld_dly1 : std_logic;
    signal d_vld_dly2 : std_logic;
begin
    D_VLD_i <= D_VLD;

    process (clk) is
    begin
        if rising_edge(clk) then
            d_vld_dly1 <= D_VLD;
            d_vld_dly2 <= D_VLD_i;
        end if;
    end process ;

    Q_VLD1 <= d_vld_dly1;
    Q_VLD2 <= d_vld_dly2;
end Behavioral;


ENTITY tb_assign_test IS
END tb_assign_test;
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