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VHDL 案例选择不是局部静态的

此代码适用于一些工具

  • Aldec Riviera Pro

但不是其他人

  • GHDL(错误选择必须是本地静态表达式)
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY INSTRUCTION_PROCESSOR IS

    PORT (
        clk : IN std_logic;
        instruction : IN INTEGER
    );
END ENTITY INSTRUCTION_PROCESSOR;
ARCHITECTURE behavioural OF INSTRUCTION_PROCESSOR IS

    TYPE INSTRUCTION_t IS RECORD
        instr : INTEGER;
        cycles : INTEGER;
    END RECORD;

    CONSTANT CMD_A : INSTRUCTION_t := (instr => 0, cycles => 5);
    CONSTANT CMD_B : INSTRUCTION_t := (instr => 1, cycles => 3);

BEGIN
    PROCESSOR : PROCESS (clk)
        VARIABLE loop_cycles : INTEGER := 0;
    BEGIN …
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vhdl ghdl

2
推荐指数
1
解决办法
416
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ghdl ×1

vhdl ×1