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我试图减去2 std逻辑向量并得到错误

p2 <= p1(11 downto 0)- idata(11 downto 0);

错误(10327):sub.vhd(32)处的VHDL错误:无法确定运算符""的定义 - "" - 找到0个可能的定义

我已经尝试添加use IEEE.std_logic_signed.all或 use IEEE.std_logic_unsigned.all或两者已经尝试过 p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use IEEE.std_logic_signed.all;
--use IEEE.std_logic_unsigned.all;

entity sub is 

port (  
    clk         : in    std_logic;
    rst         : in    std_logic;
    --en            : in    std_logic;  
    idata    : in    std_logic_vector (11 downto 0);
    odata    : out  std_logic_vector (11 downto 0)  
);
end sub;

architecture beh of sub is …