我不确定我是否从以下地方了解如何使用getVerilog函数：https : //github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb
[error] passthrough_test.scala:18:11: not found: value getVerilog
[error] println(getVerilog(new PassThrough(10)))
[error] ^
[error] one error found
[error] (Test / compileIncremental) Compilation failed
[error] Total time: 1 s, completed Nov 21, 2018 1:53:02 PM
我确实导入了chisel3._，但这似乎还不够。
chisel ×1