以下VHDL将用于测试工作台.在分析期间,我在第一个等待语句中一直出现错误:"wait语句必须包含带有UNTIL关键字的条件子句"我有几个以这种方式编写的工作测试平台.我似乎无法找到错误可能是什么.
`library IEEE;
USE IEEE.std_logic_1164.all;
entity case_ex_TB is end;
architecture simple_test of case_ex_TB is
--- DUT Component Declaration ---
component case_ex
port(
clk, rstN: IN std_logic;
color: OUT std_logic_vector(2 downto 0));
end component;
--- Signals Declaration ---
signal rst, clock: std_logic:='0';
signal color: std_logic_vector(2 downto 0);
begin
DUT: case_ex --- DUT instantiation ---
port map (clk => clock,
rstN => rst,
color => color);
--- Signal's Waves Creation ---
rst <= '1','0' after 50 ns, '1' after 2 us;
clock_crtate: …