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for-generate内部进程vhdl

我知道在进程中编写for-generate是不可能的,但是我想实现代码所呈现的功能.它基本上是一个地址解码器.任何帮助表示赞赏.

以下代码给出了语法错误:"生成附近的语法错误"

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity address_decoder is
generic (CAM_DEPTH: integer := 8);
port (in_address: in std_logic_vector(CAM_DEPTH-1 downto 0);
        out_address: out std_logic_vector(2**CAM_DEPTH-1 downto 0);
        clk : in std_logic;
        rst: in std_logic
    );
end address_decoder;

architecture Behavioral of address_decoder is

begin
decode_process:
process(clk,rst) begin

if(clk'event and clk='1') then
        if (rst = '1') then
            out_address <= (others => '0');
        else
            NAME: for i in 0 to 10 generate
                if (i = to_integer(unsigned(in_address))) then
                    out_address(i) <= '1';
            else
                    out_address(i) <= …
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vhdl

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