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如何在 VHDL 中初始化 std_logic_vector?

我有一个 std_logic_vector(4096 downto 0) 信号,我想像下面这样初始化它:

architecture Behavioral of test is

    type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
    signal ram : ram_type;
    ram(0) := "0010000000000100";   
    ram(1) := "0001000000000101";
    ram(2) := "0011000000000110";
    ram(3) := "0111000000000001";
    ram(4) := "0000000000001100";
    ram(5) := "0000000000000011";
    ram(6) := "0000000000000000";
    ram(4095 downto 7) := (others => (others => '0'));
    begin
   "some code"
end behavioral
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由于某种原因,我需要用这些值初始化它(我无法将这些值分配给它,它必须被初始化)是否有任何方法可以做到这一点?我尝试了上面的代码,但它不起作用

vhdl hdl xilinx-ise

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