小编use*_*233的帖子

我是verilog HDL的新手,我对数字电路没有经验.我从互联网上学到了一两件事,现在我正在尝试为一个计数器脚本编写测试台脚本.我从以下网站获得了反脚本:

http://www.asic-world.com/verilog/verilog_one_day2.html#Variable_Assignment

计数器:

module counter(clk,rst,enable,count);
input clk, rst, enable;
output [3:0] count;
reg [3:0] count;

always @(posedge clk or posedge rst) begin 
if (rst) begin
    count <= 0;                 
end 
else begin: COUNT           
        while (enable) begin
            count <= count + 1;
            disable COUNT;
        end
end
end
endmodule

然后我写了一个测试台如下:

试验台

// counter test bench
`timescale 1ns/100ps
module counter_tb;

    reg clk_in;         // using wire won't let value to change inside initial blcok
    reg rst_in;
    reg enable_in;
    reg[3:0] count_out;

    counter counter_uut(.clk(clk_in), .rst(rst_in), .enable(enable_in), …