我试着写一些像(在verilog中)的代码:
parameter N = 128;
if (encoder_in[0] == 1) begin
23 binary_out = 1;
24 end else if (encoder_in[1] == 1) begin
25 binary_out = 2;
26 end else if (encoder_in[2] == 1) begin
27 binary_out = 3;
28 end else if (encoder_in[3] == 1) begin
29 binary_out = 4;
30 end else if (encoder_in[4] == 1) begin
31 binary_out = 5;
32 end else if (encoder_in[5] == 1) begin
33 binary_out = 6;
34 end else if (encoder_in[6] == …Run Code Online (Sandbox Code Playgroud) verilog ×1