小编Moh*_*ati的帖子

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

- 实体部分包含R输出寄存器

entity register_16 is
    port(   input:  in std_logic_vector(15 downto 0);
        ld, inc, clk, clr:  in std_logic;
        R: buffer std_logic_vector(15 downto 0));
end register_16 ;

- 它必须并行处理

architecture behavioral of register_16 is
begin


reg: process (input, ld, clk, clr)
    variable R_temp : std_logic_vector(15 downto 0);
begin
    if (clr='1') then
        R_temp := b"0000000000000000";
    elsif (clk'event and clk='1') then
        if (ld='1') then
            R_temp := input;
        end if;
    end if;
    R <= R_temp; …