小编Lê *_*Hòa的帖子

任何人都可以帮我编写以下代码的verilog测试平台代码!我试过但它不起作用!

module top(clock_in, Reset, Hold, up_down, Led_Out, f);     
  input clock_in, Reset, Hold, up_down;
  output      [6:0] Led_Out;        
  output wire [3:0] f;

  wire pulse;

  clock_design temp0(clock_in, pulse);
  up_down_counter temp1(pulse, Reset, Hold, up_down, f);
  led7 temp2(Led_Out, f);
endmodule

led7:

module led7(iOut, iQ);
  output reg [6:0] iOut;
  input      [3:0] iQ;

  always @(iQ)
    case (iQ)
      4'b0000: iOut = 7'b0000001; //0
      4'b0001: iOut = 7'b1001111; //1
      4'b0010: iOut = 7'b0010010; //2
      4'b0011: iOut = 7'b0000110; //3
      4'b0100: iOut = 7'b1001100; //4
      4'b0101: iOut = 7'b0100100; //5 …