我正在请求一些帮助,因为我完全陷入了我的VHDL项目,包括在Nios II上实现笛卡尔到极坐标转换器.我的所有VHD文件都编译没有错误,但是当我想在Modelsim上模拟整个块时,这就是我得到的
# Loading work.counter(a)
# ** Failure: (vsim-3807) Types do not match between component and entity for port "rn".
# Time: 0 ps Iteration: 0 Instance: /bench_conversor/uut/compt File: C:/Users/Sandjiv/Desktop/test_VHDL/counter.vhd Line: 23
# ** Failure: (vsim-3807) Types do not match between component and entity for port "thetan".
# Time: 0 ps Iteration: 0 Instance: /bench_conversor/uut/compt File: C:/Users/Sandjiv/Desktop/test_VHDL/counter.vhd Line: 24
# Fatal error in file C:/Users/Sandjiv/Desktop/test_VHDL/counter.vhd
# while elaborating region: /bench_conversor/uut/compt
# Load interrupted
这应该是很容易发现的错误,但我检查了我的类型一千次,它们似乎都匹配.这里遵循计数器,转换器(整个块)及其工作台的代码.他们再一次编译,但我只在Modelsim的模拟中得到这些错误.
COUNTER.VHD
library ieee;
use ieee.std_logic_1164.all;
use …