标签: tilera

在TILE-Gx架构的Linux内核自旋锁实现中,看起来它们在锁定时不会发出任何内存障碍(仅在解锁时):

https://github.com/torvalds/linux/blob/master/arch/tile/include/asm/spinlock_64.h

然后我不明白为什么指令不能在锁定之上重新排序,这会导致程序员认为在保持锁定时执行的指令,在锁定之前实际执行？

其他架构似乎至少有一个编译器障碍:

• ARM的自旋锁具有内存屏障:

  https://github.com/torvalds/linux/blob/master/arch/arm/include/asm/spinlock.h

  评论:

  A memory barrier is required after we get a lock, and before we 
  release it, because V6 CPUs are assumed to have weakly ordered 
  memory.
  

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• x86的spinlock有一个编译器障碍:

  https://github.com/torvalds/linux/blob/master/arch/x86/include/asm/spinlock.h

  评论:

  barrier();     /* make sure nothing creeps before the lock is taken */
  

  Run Code Online (Sandbox Code Playgroud)

为什么TILE-Gx不同？我认为它的内存模型和ARM的内存模型一样弱.为什么他们甚至没有编译器障碍？