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如何安排Makefile来编译带有多个.c文件的内核模块？

这是我当前的Makefile.它是由KDevelop自动生成的

TARGET = nlb-driver
OBJS = nlb-driver.o
MDIR = drivers/misc

EXTRA_CFLAGS = -DEXPORT_SYMTAB
CURRENT = $(shell uname -r)
KDIR = /lib/modules/$(CURRENT)/build
PWD = $(shell pwd)
DEST = /lib/modules/$(CURRENT)/kernel/$(MDIR)

obj-m += $(TARGET).o

default:
    make -C $(KDIR) M=$(PWD) modules

$(TARGET).o: $(OBJS)
    $(LD) $(LD_RFLAG) -r -o $@ $(OBJS)

ifneq (,$(findstring 2.4.,$(CURRENT)))
install:
    su -c "cp -v $(TARGET).o $(DEST) && /sbin/depmod -a"
else
install:
    su -c "cp -v $(TARGET).ko $(DEST) && /sbin/depmod -a"
endif

clean:
    -rm -f *.o *.ko .*.cmd .*.flags …