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我是VHDL的新手,我正试图弄清楚如何在Altera Cyclone II上做一些相当基本的事情.FPGA有四个按钮 - 其中两个需要编程以增加和减少所选寄存器(0-F),两者需要编程以增加和减少将在注册.这是我到目前为止:

entity raminfr is
    port (
        clk : in std_logic;
        we : in std_logic;
        a : in unsigned(3 downto 0);
        di : in unsigned(7 downto 0);
        do : out unsigned(7 downto 0)
    );
end raminfr;

architecture rtl of raminfr is
type ram_type is array (0 to 15) of unsigned(7 downto 0);
signal RAM : ram_type;
signal read_a : unsigned(3 downto 0);

begin

process (clk)
begin
    if rising_edge(clk) then
        if we = '1' then
            RAM(to_integer(a)) <= di; …