我可以在循环中生成许多SystemVerilog属性吗？

Question

我有两个打包的信号数组,我需要为该属性创建一个属性和相关的断言,证明这两个数组在某些条件下是相同的.我正式验证并且该工具无法在单个属性中证明两个完整数组,因此我需要将其拆分为单个元素.那么有没有办法可以使用循环为数组的每个元素生成属性？目前,我的代码非常冗长,难以导航.

我的代码目前看起来像这样:

...
property bb_3_4_p; 
  @(posedge clk)
     bb_seq  
     |=>     
     bb_exp [3][4] == bb_rtl [3][4] ;
endproperty

property bb_3_5_p; 
  @(posedge clk)
     bb_seq  
     |=>     
     bb_exp [3][5] == bb_rtl [3][5] ;
endproperty

property bb_3_6_p; 
  @(posedge clk)
     bb_seq  
     |=>     
     bb_exp [3][6] == bb_rtl [3][6] ;
endproperty
...

...
assert_bb_3_4: assert property (bb_3_4_p);
assert_bb_3_5: assert property (bb_3_5_p);
assert_bb_3_6: assert property (bb_3_6_p);
...

这就像我希望我的代码看起来像:

for (int i = 0; i < 8; i++) 
  for (int j = 0; j < 8; j++) 
  begin   
     property bb_[i]_[j]_p;
        @(posedge clk)
           bb_seq  
           |=>     
           bb_exp [i][j] == bb_rtl [i][j] ;
     endproperty
     assert_bb_[i]_[j]: assert property (bb_[i]_[j]_p);
  end     

Answer 1

您可以尝试使用端口声明属性,以便可以将其重用于多个断言.然后使用generate循环声明你的断言.

module
...
property prop1(signal1,signal2); 
  @(posedge clk)
     bb_seq  
     |=>     
     signal1 == signal2 ;
endproperty
...
generate
for (genvar i = 0; i < 8; i++) 
  for (genvar j = 0; j < 8; j++) 
    begin : assert_array
    assert property (prop1(bb_exp[i][j],bb_rtl[i][j]));
    end
endgenerate
... 
endmodule

您还可以在断言中内联属性:

module
...
generate
for (genvar i = 0; i < 8; i++) 
  for (genvar j = 0; j < 8; j++)
    begin : assert_array
    assert property (@(posedge clk) bb_seq |=> bb_exp[i][j] == bb_rtl[i][j]);
    end
endgenerate
...
endmodule