Tick Counter Verilog

Question

我想知道如何为滴答计数器编写verilog程序.当快速输入为低电平时,输出标记为每150 ms一个周期为高(每7500 000个周期)clk周期为20ns.如果快速输入为高电平,则每隔一个时钟周期,tick应该变为高电平一个周期.

我在想我应该计算clk周期,并在满足周期数时使用计数输出滴答,但我似乎无法使其工作.

继承我的代码:

module tick_counter(
  input  clk,
  input  reset,
  input  fast,
  output reg tick
);

reg count;

always @(posedge clk) begin
  count <= count + 1;
  if((fast == 1)&&(count == 2)) begin
    tick <= 1;
  end
  else if(fast == 0)&&(count == 7500000)) begin
    tick <= 1;
  end
end
endmodule

Answer 1

您的计数器只有 1 位宽，您没有包括重置，您也没有在需要时将计数器归零。==2 只是 == 7500000 的相移。尝试：

module tick_counter(
  input  clk,
  input  reset,
  input  fast,
  output reg tick
);

reg [22:0] count;

always @(posedge clk or negedge reset) begin
  if (~reset) begin
    count <= 'd0;
    tick  <=   0;
  end
  else begin
    if((fast == 1)&&(count == 2)) begin
      tick  <= 1;
      count <= 'd0;
    end
    else if(fast == 0)&&(count == 7500000)) begin
      tick  <= 1;
      count <= 'd0;
    end
    else begin
      tick  <= 0;
      count <= count + 1;
    end
  end
end
endmodule

或者像下面这样的东西可能会合成得更小：

reg  [22:0] count;

wire [22:0] comp = (fast) ? 23'd2: 23'd7500000 ;
wire        done = count >= comp               ;

always @(posedge clk or negedge reset) begin
  if (~reset) begin
    count <= 'd0;
    tick  <=   0;
  end
  else begin
    if(done) begin
      tick  <= 1;
      count <= 'd0;
    end
    else begin
      tick  <= 0;
      count <= count + 1;
    end
  end
end