来自不同过程的VHDL驱动信号

Question

我对以下VHDL代码有一点问题:

process (zbroji)
begin
    if rising_edge(zbroji) then
        oduzima <= '0';
        ucitanPrvi <= '1';
        broj1 <= ulaz_broj;
    end if;
end process;

process (oduzmi)
begin
    if rising_edge(oduzmi) then
        oduzima <= '1';
        ucitanPrvi <= '1';
        broj1 <= ulaz_broj;
    end if;

end process;

问题是信号ucitanPrvi总是有值X.如果我不尝试在两个进程中设置它的值,那么我没有任何问题...所以我知道我不能从多个进程驱动一个信号,但我不知道如何以不同的方式写这个...有谁知道如何解决这个问题？

谢谢 !

编辑:谢谢大家回复:)现在我明白为什么我不能从多个进程驱动一个信号(至少在我希望它工作的方式).

Answer 1

如果您想要为真正的FPGA或ASIC综合您的设计,您将不得不考虑真实硬件(电线,触发器,门等)的VHDL.此外,如果要在硬件中执行真正的上升沿检测,则需要一个驱动触发器的系统时钟.鉴于您的原始代码示例,zbroji或oduzmi似乎不是系统时钟,而只是std_logic信号.我编写了这个代码示例,假设您的示例中有基本功能,希望您可以获取我的代码和注释并完成您的需要.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example is
  port (Reset      : in  std_logic;
        SysClk     : in  std_logic;
        zbroji     : in  std_logic;
        oduzmi     : in  std_logic;
        ulaz_broj  : in  std_logic;
        oduzima    : out std_logic;
        ucitanPrvi : out std_logic;
        broj1      : out std_logic
        );

end example;

architecture Behavioral of example is

  -- Delayed version of input signals (1 clock cycle delay)
  signal zbroji_d : std_logic;
  signal oduzmi_d : std_logic;

  signal zbrojiRE : std_logic;
  signal oduzmiRE : std_logic;

begin

  -- Generate 1 clock cycle delayed version of
  -- signals we want to detect the rising edge
  -- Assumes active high reset
  -- Note: You should only use the rising_edge macro
  -- on an actual global or regional clock signal. FPGA's and
  -- ASICs place timing constraints on defined clock signals
  -- that make it possible to use rising_edge, otherwise, we have
  -- to generate our own rising edge signals by comparing delayed
  -- versions of a signal with the current signal.
  -- Also, with any respectable synthesizer / simulator using
  -- rising_edge is almos exactly the same as (clk'event and clk='1')
  -- except rising_edge only returns a '1' when the clock makes a
  -- valid '0' to '1' transition. (see link below)
  EdgeDetectProc : process (Reset, SysClk)
  begin
    if Reset = '1' then
      zbroji_d <= '0';
      oduzmi_d <= '0';
    elsif rising_edge(SysClk) then
      zbroji_d <= zbroji;
      oduzmi_d <= oduzmi;
    end if;
  end process EdgeDetectProc;

  -- Assert risinge edge signals for one clock cycle 
  zbrojiRE <= '1' when zbroji = '1' and zbroji_d = '0' else '0';
  oduzmiRE <= '1' when oduzmi = '1' and oduzmi_d = '0' else '0';

  -- Assumes that you want a single cycle pulse on ucitanPrvi on the
  -- rising edege of zbroji or oduzmi;
  ucitanPrvi <= zbrojiRE or oduzmiRE;

  -- Based on your example, I can't tell what you want to do with the
  -- broj1 signal, but this logic will drive broj1 with ulaz_broj on
  -- either the zbroji or oduzmi rising edge, otherwise '0'.
  broj1 <= ulaz_broj when zbrojiRE = '1' else
           ulaz_broj when oduzmiRE = '1' else
           '0';

  -- Finally, it looks like you want to clear oduzima on the rising
  -- edge of zbroji and assert oduzima on the rising edge of
  -- oduzmi
  LatchProc : process (Reset, SysClk)
  begin
    if Reset = '1' then
      oduzima <= '0';
    elsif rising_edge(SysClk) then
      if zbrojiRE = '1' then
        oduzima <= '0';
      elsif oduzmiRE = '1' then
        oduzima <= '1';
      end if;
    end if;
  end process LatchProc;

end Behavioral;

前面的代码假设您有一个系统时钟.在像ModelSim(免费学生版)这样的模拟器中,您可以使用不可合成的测试平台代码生成100 MHz时钟,如下所示......

ClockProc : process
begin 
   SysClk <= '0';
   wait for 5 ns;
   SysClk <= '1';
   wait for 5 ns;
end process ClockProc;

在实际的FPGA/ASIC实现中,您可能希望使用插入芯片的外部振荡器,将信号驱动到DCM(数字时钟管理器),这将向您的所有VHDL逻辑输出非常干净的时钟信号. ,所以你可以有一个无故障的设计.

最后,这里是关于rising_edge和(clk'event和clk ='1')之间差异的一个很好的解释

http://vhdlguru.blogspot.com/2010/04/difference-between-risingedgeclk-and.html

希望有所帮助.