在IBM Z（s390x）上超过4K（页面大小）的指令如何以基址+偏移量方式寻址？

Question

我们知道每条指令都转换为基址+偏移量，并且偏移量最大大小设置为4K（4096）。如果我的程序大小超过 4k 怎么办？

Line 1 : Base  + 1 , 
Line 2 : Base  + 5 , 
.
.
.
., 
Line x : base + 4090 

当指令超出页面大小 4096 时，如何对第 x 行开始进行寻址（如基址 + 偏移量）？

从 X 行开始的指令是如何组装的？我们是否需要将基地址更改为保存指令的下一页的开头？

Answer 1

使用 IBM 大型机处理器进行寻址

今天的 z/Architecture（IBM 大型机）处理器的祖先确实只提供基址偏移寻址。您必须将基址加载到寄存器中，然后指定该基址寄存器加上 12 位偏移量，即 0 到 4095 字节来寻址某些存储。

使用 S390/Architecture 处理器寻址

汇编器提供了USING帮助您完成此操作的说明。您在程序和寄存器中指定一个标签，该寄存器将在运行时保存该标签指令的地址。然后汇编器将为您计算偏移量。

例子

         ...
         LA    R5,SUB01
         BALR  R4,R5
         ...
SUB01    DS 0H
         USING SUB01,R5
         ...
         B     SUB01A
         ...
SUB01A   DS    0H

说明：在程序的某个地方，您需要调用 subroutine SUB01。将其地址加载到寄存器 5 ( R5) 中，然后进行分支，同时将返回地址保存到寄存器 4 ( R4) 中。这就是说明LA R5,SUB01和BALR R4,R5操作的内容。

In your subroutine, you tell the assembler that R5 is pointing to the address SUB01 with the USING SUB01,R5. The assembler uses this information to build the branch instruction B SUB01A. It calculates the offset from SUB01 to SUB01A.

If the code starting at SUB01 is longer than 4096 bytes, the maximum offset, you need a second, third, fourth, etc register, which point to the next 4k segment, each.

Assuming the code is 10k long, you need three registers. The code might look like this:

         ...
         LA    R5,SUB01
         BALR  R4,R5
         ...
SUB01    DS 0H
         LA    R6,4095(,R5)    
         LA    R6,1(,R6)
         LA    R7,4095(,R6)    
         LA    R7,1(,R7)
         USING SUB01,R5,R6,R7
         ...
         B     SUB01A
         ...
SUB01A   DS    0H

Explanation: Upon entry to SUB01 you know that R5 point to that label. You need to load R6 with R5 + 4096, and R7 with R5 + 8192. There are different ways to achieve this. I'm showing the one using the load address LA instruction, which has a maximum offset of 4095 (architecture restriction).

The you tell the assembler that registers R5, R6, and R7 can be used to calculate the offsets. It will use R5 if the offset is 0-4095, R6 if the offset is 4096-8191, and R7 of the offset is 8192-12287.

Addressing with z/Architecture processors

With z/Architecture, IBM introduced a set of new instructions that use a 20-bit signed displacement. Those instructions use a signed offset, i.e they can address storage after the address in the base register, but also storage before that address. A 20-bit signed offset provides for relative addressing of up to 524,287 bytes beyond the base address location or of up to 524,288 bytes before it.

You can address much larger areas with those instruction using a single base register.

IBM z/Architecture Description

IBM documents its z/Architecture in a manual called z/Architecture Principles of Operation