VCD仅通过modelsim转储设计的子部分

Question

我有一个很大的设计,包括测试平台,一些测试电路和被测电路本身.我使用modelsim来模拟设计,我希望有一个模拟转储.我被建议使用以下命令生成转储:

vcd file myvcd1.vcd
vcd add -r /sim_minimips/*

它接缝工作,但我想要的是只为被测电路生成转储.

我试图使用相同的命令来指定我想要考虑的文件的名称:

vcd file myvcd2.vcd
vcd add -r /minimips/*

但是生成了以下错误:

Error vsim 3561 No object matching minimips

我不明白错误,我不确定即使这是隔离子部分的正确程序.

有谁知道怎么做或知道我在哪里可以得到一个关于这个价值变化转储的体面的简单教程？

我附上我的测试台实体:

library IEEE;
use IEEE.std_logic_1164.all;

library std;
use std.textio.all;

library work;
use work.pack_mips.all;

entity sim_minimips is
end;

architecture bench of sim_minimips is

  component minimips is
  port (
      clock    : in std_logic;
      reset    : in std_logic;

      ram_req  : out std_logic;
      ram_adr  : out bus32;
      ram_r_w  : out std_logic;
      ram_data : inout bus32;
      ram_ack  : in std_logic;

      it_mat   : in std_logic
  );
  end component;


  component ram is
    generic (mem_size : natural := 256;
             latency : time := 10 ns);
    port(
        req        : in std_logic;
        adr        : in bus32;
        data_inout : inout bus32;
        r_w        : in std_logic;
        ready      : out std_logic
  );
  end component;

  component rom is
  generic (mem_size : natural := 256;
           start : natural := 0;
           latency : time := 10 ns);
  port(
          adr : in bus32;
          donnee : out bus32;
          ack : out std_logic;
          load : in std_logic;
          fname : in string
  );
  end component;

  signal clock : std_logic := '0';
  signal reset : std_logic;

  signal it_mat : std_logic := '0';

  -- Connexion with the code memory
  signal load : std_logic;
  signal fichier : string(1 to 7);

  -- Connexion with the Ram
  signal ram_req : std_logic;
  signal ram_adr : bus32;
  signal ram_r_w : std_logic;
  signal ram_data : bus32;
  signal ram_rdy : std_logic;

begin

    U_minimips : minimips port map (
        clock => clock,
        reset => reset,
        ram_req => ram_req,
        ram_adr => ram_adr,
        ram_r_w => ram_r_w,
        ram_data => ram_data,
        ram_ack => ram_rdy,
        it_mat => it_mat
    );

    U_ram : ram port map (
        req => ram_req,
        adr => ram_adr,
        data_inout => ram_data,
        r_w => ram_r_w,
        ready => ram_rdy
    );

    U_rom : rom port map (
        adr => ram_adr,
        donnee => ram_data,
        ack => ram_rdy,
        load => load,
        fname => fichier
    );

    clock <= not clock after 20 ns;
    reset <= '0', '1' after 5 ns, '0' after 70 ns;
    ram_data <= (others => 'L');

    process
        variable command : line;
        variable nomfichier : string(1 to 3);
    begin
        write (output, "Enter the filename : ");
        readline(input, command);
        read(command, nomfichier);

        fichier <= nomfichier & ".bin";

        load <= '1';
        wait;
    end process;

    -- Memory Mapping
    -- 0000 - 00FF      ROM

    process (ram_adr, ram_r_w, ram_data)
    begin -- Emulation of an I/O controller
        ram_data <= (others => 'Z');

        case ram_adr is
            when X"00001000" => -- program an interrupt after 1000ns
                                it_mat <= '1' after 1000 ns;
                                ram_rdy <= '1' after 5 ns;
            when X"00001001" => -- clear interrupt line on cpu
                                it_mat <= '0';
                                ram_data <= X"FFFFFFFF";
                                ram_rdy <= '1' after 5 ns;
            when others      => ram_rdy <= 'L';
        end case;
    end process;

end bench;

干杯,Ste

Answer 1

最后一个参数vcd add是您要添加的信号的设计层次路径(使用实例名称)(*表示所有信号,尽管-r信号也会扩展到您指定的层次结构下面的设计的所有级别) ).

因此,如果您使用实例名称进行实例minimips化,则添加(特定)所有信号的正确方法以及它可能实例化的任何块都是sim_minimipsi_minimipsminimips

vcd add -r /sim_minimips/i_minimips/*

如果你想限制的项目添加到VCD远一点,你可以添加参数的一个或多个-in,-inout,-out,-internal或者-ports,其中仅选择这些类型的项目.或者忽略-r不进入层次结构 - 常见的用法是vcd add -ports /sim_minimips/minimips/*仅添加设计顶层的端口,适合为多种类型的测试台生成刺激.

应该注意的是,vcd add"正好"工作wave add,即对象规范的格式完全相同.因此,向VCD添加项目的最简单方法通常是将它们添加到Modelsim UI中的wave中,从脚本中复制粘贴命令,然后简单地将其更改wave add为a vcd add.

此外,文件名在这里没有任何影响,只有设计本身的结构.例如,如果你有类似的东西:

entity sim_minimips is
    port (
        -- ...
    );
end sim_minimips;

entity minimips is
    port (
        -- ...
    );
end minimips;

architecture tb of sim_minimips is
    component minimips
        port (
            -- ...
        );
    end component;
begin
    I_MINIMIPS: minimips
        port map (
            -- ...
        );
end architecture tb;

在这种情况下,您的minimips实例的路径是/sim_minimips/I_MINIMIPS/.