在VHDL文件之间共享(包括？)泛型？

Question

假设我有这个简单的核心与泛型genertest.vhd:

--------------------------------------------------------------------------
library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  -- use IEEE.STD_LOGIC_ARITH.ALL;
  -- use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use IEEE.NUMERIC_STD.ALL;


ENTITY genertest IS
  GENERIC(
    numbits : natural := 8
  );
  PORT
  (
    clk   :  IN STD_LOGIC;
    d_OUT : OUT STD_LOGIC_VECTOR(numbits-1 downto 0);
    d_IN  :  IN STD_LOGIC_VECTOR(numbits-1 downto 0)
  );
END genertest;


ARCHITECTURE structure OF genertest IS
BEGIN

  main_proc: PROCESS(clk)
  BEGIN
    IF rising_edge(clk) THEN -- posedge
      d_OUT <= not(d_IN);
    END IF;
  END PROCESS main_proc;

END structure;

...我想用以下测试工作台测试它genertest_twb.vhd:

----------------------------------------------------------------------------------

library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  -- use IEEE.STD_LOGIC_ARITH.ALL;
  -- use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use IEEE.NUMERIC_STD.ALL;

ENTITY genertest_twb IS
END genertest_twb;

ARCHITECTURE testbench_arch OF genertest_twb IS

  COMPONENT genertest
    PORT(
      clk   :  IN STD_LOGIC;
      d_OUT : OUT STD_LOGIC_VECTOR(numbits-1 downto 0);
      d_IN  :  IN STD_LOGIC_VECTOR(numbits-1 downto 0)
    );
  END COMPONENT;

  SIGNAL wtCLK : std_logic := '0';
  SIGNAL wCntReg : STD_LOGIC_VECTOR(numbits-1 DOWNTO 0) := (others => 'Z');
  SIGNAL tmp_cnt : natural := 0 ;

  -- clock parameters
  constant PERIODN : natural := 20; -- can be real := 20.0;
  constant PERIOD : time := PERIODN * 1 ns;
  constant DUTY_CYCLE : real := 0.5;
  constant OFFSET : time := 100 ns;

BEGIN

  UUT : genertest -- VHDL
  PORT MAP(
    clk => wtCLK,
    d_IN => wCntReg,
    d_OUT => OPEN
  );

  -- clock process for generating CLK
  -- (here, left as unnamed)
  PROCESS
  BEGIN

    WAIT for OFFSET;

    CLOCK_LOOP : LOOP
      wtCLK <= '0';
      -- tmp_na - natural problems with bit width?
      -- wCntReg <= std_logic_vector(to_unsigned(natural'pos(tmp_na), wCntReg'length));
      WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
      wtCLK <= '1';
      WAIT FOR (PERIOD * DUTY_CYCLE);
    END LOOP CLOCK_LOOP;
  END PROCESS;


  count_proc: PROCESS(wtCLK)
  BEGIN
    IF rising_edge(wtCLK) THEN -- posedge
      tmp_cnt <= tmp_cnt + 1;
      wCntReg <= std_logic_vector(to_unsigned(natural'pos(tmp_cnt), wCntReg'length));
    END IF;
  END PROCESS count_proc;


END testbench_arch;

现在,我假设通过引用genertest组件,工作台会自动了解numbits泛型,但不幸的是,情况并非如此; ISE WebPack中上述工作台的行为模拟失败:

ERROR:HDLCompiler:69 - "/genertest_tbw.vhd" Line 17: <numbits> is not declared.
ERROR:HDLCompiler:69 - "/genertest_tbw.vhd" Line 18: <numbits> is not declared.
ERROR:HDLCompiler:69 - "/genertest_tbw.vhd" Line 23: <numbits> is not declared.

通过在genertest_tbw.vhd这里添加通用部分:

  COMPONENT genertest
    GENERIC(
      numbits : natural := 8
    );
    PORT(
      ...

...将修复组件本地的泛型引用 - 遗憾的是,SIGNAL wCntReg声明中对泛型的引用仍然会失败.

最后,在genertest_tbw.vhd这里添加通用部分:

ENTITY genertest_twb IS
  GENERIC(
    numbits : natural := 8
  );
END genertest_twb;

...使通用可用于整个工作台文件.

但是,这仍然意味着我必须numbits : natural := 8在工作台文件中手动复制/粘贴句子; 这意味着它将计算两个地方,如果我想更改通用值,我必须更改两个:(

所以我的问题是 - 有没有办法共享/包含泛型,这样它们只能在一个文件中编写/定义 - 而其他文件可以引用这些特定的值？

提前感谢任何答案,
干杯!

Answer 1

你错过了泛型的观点.您不会通过层次结构传递通用值,而是将它们传递下来.

在测试平台中定义numbits(可能更有意义,比如RAM_WIDTH),并使用它来用适当的位数实例化genertest.为genestest实体中的numbits定义的默认值用于未明确定义泛型值的代码(为了可读性,或者为了保持以前总是占用8位的函数的向后兼容性,但现在可以配置为任何宽度).

因此,在您的测试平台中,您需要以下内容:

constant RAM_WIDTH : integer := 8;
...
UUT : genertest 
  GENERIC MAP (
    numbits => RAM_WIDTH
  );
  PORT MAP
  (
    clk   => wtCLK,
...