Vivado：警告时序时钟 (TIMING-17) 未到达时钟引脚 x_reg.C

Question

我正在尝试使用 Xilinx 的 Vivado 工具编译一些 FPGA 代码。但是，当我运行“综合”然后选择“报告方法”时......我得到以下不良实践列表：

TIMING-17
TIMING #1 Warning The clock pin last_anthony_reg.C is not reached by a timing clock 
TIMING #2 Warning The clock pin last_paul_reg.C is not reached by a timing clock 
TIMING #3 Warning The clock pin last_steven_reg.C is not reached by a timing clock 

我想知道是什么导致了这个“警告”消息...我尝试查看原理图...但对我来说看起来不错...只看到 FDCE 和一些 LUTS，那里没有什么异常。

这是我的 FPGA 顶层 VHDL 实体：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example1 is
    port(
        clk           :in    std_logic;
        clear         :in    std_logic;

        richard       :out   std_logic;
        james         :in    std_logic;
        michael       :in    std_logic;
        william       :out   std_logic;       
        david         :out   std_logic;       
        robert        :in    std_logic
    );
end entity;

VHDL 架构：

architecture rtl of example1 is
    signal matthew                :std_logic_vector(1 downto 0);
    signal anthony, last_anthony  :std_logic;
    signal steven,  last_steven   :std_logic;
    signal paul,    last_paul     :std_logic;    
begin

process(clk)
begin
    if (rising_edge(clk)) then
        last_anthony <= anthony;
        last_steven  <= steven;
        last_paul    <= paul;
    end if;
end process;

matthew <= (michael and not last_paul) & (robert and not last_steven);

process(
    clear,
    matthew,
    james,    
    last_anthony,
    last_steven,
    last_paul    
)
begin

    if (clear = '1') then
        anthony  <= '0';
        steven   <= '0';
        paul     <= '1';          
    else
        --defaults

        case matthew is

        when "00" =>
            anthony  <= james;
            steven   <= '1';
            paul     <= '0';

        when "01" =>
            anthony  <= last_anthony;
            steven   <= last_steven;
            paul     <= last_paul;

        when "10" =>
            anthony  <= james;
            steven   <= '1';
            paul     <= '0';

        when "11" =>
            anthony  <= last_anthony;
            steven   <= '0';
            paul     <= '1';

        --synthesis translate_off                
        when others =>
            anthony  <= 'X';
            steven   <= 'X';
            paul     <= 'X';
        --synthesis translate_on

        end case;            
    end if;
end process;

william   <= steven;
david     <= paul;
richard   <= anthony;    

end architecture;

Answer 1

vivado 不能仅根据哪个信号将进入“thoughtge”或“rising_edge”语句来推断哪个信号是时钟吗？

Vivado 知道所有时钟是什么（毕竟它会在时钟引脚上向您发出警告），但它不知道该时钟的参数：频率、占空比等。这就是它抱怨的：通过以下方式到达引脚时钟，但不是具有计时信息的时钟：“计时时钟”。

您必须在约束文件中指定这些内容，例如：

# define ext pll clock as 100 MHz for timing check
create_clock -period 10.000 -name ext_pll_in [get_ports PL_HP66]

我知道有一个“约束向导”，但我从未使用过它。
运行综合后，您将进入“约束向导”选项，然后“打开综合设计”。