VHDL - 带反馈的相位累加器

Question

我正在尝试使用具有以下特征的VHDL创建相位累加器.

输入:

• D(输入信号)
• 重启
• CE
• CLK

输出:

• Q(输出信号 - 反馈)

源代码:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Phase_accu is
port (
    D       : in std_logic_vector(3 downto 0);
    CE      : in std_logic;
    CLK     : in std_logic;
    RESET   : in std_logic;
    Q       : out std_logic_vector(15 downto 0)
);
end Phase_accu;

architecture Behavioral of Phase_accu is
begin

process(D, CE, CLK, RESET)
    begin
        if RESET = '1' then
            Q <= "0000000000000000";
        elsif rising_edge(CLK) then
            if CE = '1' then
                Q <= ("000000000000" & D) + Q;
            end if;
        end if;
end process;

end Behavioral;

线路试图将2个信号合并在一起以获得反馈,我收到错误...

Q <= ("000000000000" & D) + Q;

无法读取输出"Q".

Answer 1

out在VHDL-2008之前,您无法读取VHDL版本中的值.解决此问题的常用方法是获得输出的内部副本,并在需要获取其值时使用该内部副本:

[...]
Q : out std_logic_vector(15 downto 0);
[...]
signal Q_reg : std_logic_vector(15 downto 0);

process(D, CE, CLK, RES)
    begin

        if RES = '1' then
            Q_reg <= "0000000000000000";
        elsif rising_edge(CLK) then
            if CE = '1' then
                Q_reg <= ("000000000000" & D) + Q_reg;
            end if;
        end if;
end process;

Q <= Q_reg;