如何使用 IceStorm iCE40 FPGA 流程运行综合后仿真

Question

良好的设计实践不仅可以通过常规的预综合（行为）仿真来验证 Verilog 设计，而且还可以使用综合后仿真。在调试仿真和硬件之间的不匹配时，这实际上是强制性的。如何使用 iCE40 FPGA 的开源 IceStorm 流程来实现这一目标？

Answer 1

有关示例，请参阅https://github.com/cliffordwolf/icestorm/tree/master/examples/icestick 。“rs232demo”项目附带一个测试平台，Makefile 包含综合前和综合后模拟的规则：

make rs232demo_tb.vcd      # pre-synthesis simulation
make rs232demo_syntb.vcd   # post-synthesis simulation

Use a VCD viewer like gtkwave to view the VCD files generated by this two commands.

In order to run post-synthesis simulation one must first convert the BLIF netlist (synthesis output) to a Verilog netlist: yosys -p 'read_blif -wideports example.blif; write_verilog example_syn.v'

This netlist will instantiate iCE40 device primitives. Yosys comes with simulation models for those primitives. Run the command yosys-config --datdir/ice40/cells_sim.v to print the full path name of that simulation library. Use this Verilog file when compiling your simulation.

Edit: Two additional FAQs regarding post-synthesis simulation:

(1) The clock should not have a clock edge at timestamp 0 as this can result in a race condition between clocked register updates and register initialization. I.e. the following test bench code for generating the clock is problematic:

    reg clk = 1;
    always #5 clk = ~clk;

Instead you should use something like the following, that leaves the clock signal undefined for an initial period:

    reg clk;
    always #5 clk = (clk === 1'b0);

(2) 一些信号（或向量的各个位）可以在合成过程中被优化掉。该位可以设置为恒定值（通常为x）或由工具保留为浮动值。当尝试检查综合后仿真结果时，这可能会令人困惑。设置keep您希望工具保留的网络属性：

    (* keep *) reg [31:0] foobar;