添加std_logic_vectors时出错

Question

我想要一个简单的模块,添加两个std_logic_vectors.但是,当使用下面的代码和+运算符时,它不会合成.

library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity add_module is
        port(
  pr_in1   : in std_logic_vector(31 downto 0);
  pr_in2   : in std_logic_vector(31 downto 0);
  pr_out   : out std_logic_vector(31 downto 0)  
        );
end add_module;

architecture Behavior of add_module is

begin

    pr_out <= pr_in1 + pr_in2;

end architecture Behavior;

我从XST得到的错误消息

第17行.+在这种情况下不能有这样的操作数.

我想念图书馆吗？如果可能,我不想将输入转换为自然数.

非常感谢

Answer 1

您希望编译器如何知道您的std_logic_vectors是已签名还是未签名？Adder实现在这两种情况下并不相同,因此您需要明确告诉编译器您希望它做什么;-)

注意:StackOverflow中的VHDL语法突出显示很糟糕.将此代码复制/粘贴到首选的VHDL编辑器中,以便更轻松地读取它.

library IEEE; 
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_arith.all; -- don't use this
use IEEE.numeric_std.all; -- use that, it's a better coding guideline

-- Also, never ever use IEEE.std_unsigned.all or IEEE.std_signed.all, these
-- are the worst libraries ever. They automatically cast all your vectors
-- to signed or unsigned. Talk about maintainability and strong typed language...

entity add_module is
  port(
    pr_in1   : in std_logic_vector(31 downto 0);
    pr_in2   : in std_logic_vector(31 downto 0);
    pr_out   : out std_logic_vector(31 downto 0)  
  );
end add_module;

architecture Behavior of add_module is
begin

  -- Here, you first need to cast your input vectors to signed or unsigned 
  -- (according to your needs). Then, you will be allowed to add them.
  -- The result will be a signed or unsigned vector, so you won't be able
  -- to assign it directly to your output vector. You first need to cast
  -- the result to std_logic_vector.

  -- This is the safest and best way to do a computation in VHDL.

  pr_out <= std_logic_vector(unsigned(pr_in1) + unsigned(pr_in2));

end architecture Behavior;

Answer 2

不要使用std_logic_arith- 我已经写过这个(在某种程度上:).

做使用numeric_std - 并在您的实体端口上使用正确的类型.如果您正在进行算术运算,请使用数字类型(整数或(un)符号向量,视情况而定).他们将完美地合成.

std_logic_vectors很适合

• 当你不关心数值时(一组控制位,一些随机数据位)
• 当你不知道输入的类型时(比如一个可以根据控制标志对有符号和无符号数进行操作的加法器).