为什么在将VHDL组件在其他体系结构中实例化之前需要重新声明它们？

Question

自从我的第一个VHDL课程以来,我一直在摸不着头脑,并决定在这里发布我的问题.

Given that I have a declared entity (and also an architecture of it) and want to instantiate it inside another architecture, why is it that I seemingly have to redeclare the "entity" (component) inside this containing architecture before instantiating it?

Isn't the compiler smart enough to match an instantiation to its architecture just by its name? Where is the need for the component declaration?

Answer 1

如果需要,您可以直接实例化组件:

  MyInstantiatedEntity : entity work.MyEntity_E
    generic map (
        config          => whatever)
    port map (
        clk             => signal1,
        clk_vid         => signal2,
        ...

创建组件声明使您能够通过配置规范或类似方法更改绑定到实例化的内容.