vhdl减去std_logic_vector

Question

我试图减去2 std逻辑向量并得到错误

p2 <= p1(11 downto 0)- idata(11 downto 0);

错误(10327):sub.vhd(32)处的VHDL错误:无法确定运算符""的定义 - "" - 找到0个可能的定义

我已经尝试添加use IEEE.std_logic_signed.all或 use IEEE.std_logic_unsigned.all或两者已经尝试过 p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use IEEE.std_logic_signed.all;
--use IEEE.std_logic_unsigned.all;

entity sub is 

port (  
    clk         : in    std_logic;
    rst         : in    std_logic;
    --en            : in    std_logic;  
    idata    : in    std_logic_vector (11 downto 0);
    odata    : out  std_logic_vector (11 downto 0)  
);
end sub;

architecture beh of sub is
signal p1,p2 :std_logic_vector (11 downto 0);
begin
    process (clk, rst) 
        begin
            if (rst = '1') then
                odata  <= "000000000000";
            elsif (rising_edge (clk)) then  
                    p1 <= idata;
                    p2 <= p1(11 downto 0)- idata(11 downto 0);
                    --p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));

            end if;             
    end process;
    odata<=p2;
end beh;

Answer 1

该std_logic_vector型只是一个数组std_logic,并试图在应用像减去数字运算(本身不具有任何数值的解释,从而错误-).

不要使用Synopsys非标准std_logic_signed/unsigned/arith软件包.

VHDL-2002:使用unsigned标准ieee.numeric_std包中的类型将a转换std_logic_vector为unsigned表示,允许使用数字操作,如减号.代码如:

use ieee.numeric_std.all;
...
p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));

VHDL-2008:使用标准ieee.numeric_std_unsigned包将a转换std_logic_vector为unsigned表示,允许使用数字操作,如减号.代码如:

use ieee.numeric_std_unsigned.all;
...
p2 <= p1(11 downto 0) - idata(11 downto 0);

顺便说一句.看看这个搜索类似的问题.