wait语句必须包含带UNTIL关键字的condition子句

Question

以下VHDL将用于测试工作台.在分析期间,我在第一个等待语句中一直出现错误:"wait语句必须包含带有UNTIL关键字的条件子句"我有几个以这种方式编写的工作测试平台.我似乎无法找到错误可能是什么.

`library IEEE;
USE IEEE.std_logic_1164.all;
entity case_ex_TB is end;
architecture simple_test of case_ex_TB is
--- DUT Component Declaration ---
component case_ex
    port(
    clk, rstN: IN std_logic;
    color: OUT std_logic_vector(2 downto 0));
end component;
--- Signals Declaration ---
signal rst, clock: std_logic:='0';
signal color: std_logic_vector(2 downto 0);

begin
DUT: case_ex  --- DUT instantiation ---
port map (clk => clock,
         rstN => rst,
         color => color);
--- Signal's Waves Creation ---
rst <= '1','0' after 50 ns, '1' after 2 us;
clock_crtate: process
begin
    while rst = '0' loop
        clock <= '1','0' after 50 ns;
        wait for 100 ns;
    end loop;
        clock <= '1';
        wait;
end process;
end simple_test;`

Answer 1

您收到此错误是因为您已将测试平台设置为Quartus-II中的顶级实体.顶级实体必须仍然是组件case_ex,并且此组件必须包含可合成代码.

要模拟测试平台,必须配置测试平台.只需在"RTL Simulation"之前点击加号,然后点击"编辑设置".(名称可能与Quartus版本不同).