Unable to use more than one processor group for my threads in a C# app
Eri*_*let 39 .net c# multithreading
According to MSDN documentation and Stephen Toub answer, my C# app should use every Logical Processor of every Processor Group because it is configured as required (see my App.config below).
I run my app on a windows server 2012 with a NUMA architecture: 2 x [cpu Xeon E5-2697 v3 at 14 cores each with Hyper Thread activated] => 2 x 14 x 2 = 56 Logical Processors.
My app start 80 threads either from "Thread Class" or "Parallel.For" and in both case it only takes 28 Logical Processors, all from the same Processor Group.
Why does the Task scheduler assign my threads on only one Processor Group?
我的代码可以在GitHub上找到,或者可执行文件可以在我的主页上下载
我已经在social.msdn.microsoft.com上问了这个问题而没有任何答案.
更新2015-01-26:我在connect.microsoft.com上报告了一个错误
更新2015-01-30:我添加了CoreInfo转储作为附加引用.
更新2015-01-30:问题还发生在prime95,它只提供选择28个线程(不是c#相关)
更新2015-01-30:我的工具现在显示更多信息,例如每个节点的处理器掩码.听起来我无法访问其他节点(我没有运行的节点)
更新2015-02-02,我们没有在此特定服务器上安装Citrix(抱歉,我错了)
更新2015-02-02,我们联系了惠普...
更新2015-02-03,为我的程序添加了更多信息,以显示每个线程的处理器组和更少的小工具.
更新2015-02-17,在与惠普开发团队交谈后,我更新了我的答案以反映我所学到的内容.(只是想提一下,我得到了HP的优秀支持)
更新2015-05-13,惠普在"客户咨询"说明中确认了该问题.请参阅此链接文档ID:c04650594
我将.Net 4.5(或4.5.1)App.Config设置为:
<?xml version="1.0" encoding="utf-8"?>
<configuration>
<runtime>
<Thread_UseAllCpuGroups enabled="true"></Thread_UseAllCpuGroups>
<GCCpuGroup enabled="true"></GCCpuGroup>
<gcServer enabled="true"></gcServer>
</runtime>
<startup>
<supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.5.1"/>
</startup>
</configuration>
这是来自Microsoft 的CoreInfo的转储:
Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz
Intel64 Family 6 Model 63 Stepping 2, GenuineIntel
Microcode signature: 00000023
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX * Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP * Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE * Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES * Supports AES extensions
AVX * Supports AVX intruction extensions
FMA * Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND * Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 * Supports bit manipulation extensions 1
BMI2 * Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA * Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE * Supports MOVBE instruction
ERMSB * Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID * Supports PCIDs and settable CR4.PCIDE
INVPCID * Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE * Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC * Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000F (Basic), 80000008 (Extended).
Logical to Physical Processor Map:
Physical Processor 0 (Hyperthreaded):
**------------------------------------------------------
Physical Processor 1 (Hyperthreaded):
--**----------------------------------------------------
Physical Processor 2 (Hyperthreaded):
----**--------------------------------------------------
Physical Processor 3 (Hyperthreaded):
------**------------------------------------------------
Physical Processor 4 (Hyperthreaded):
--------**----------------------------------------------
Physical Processor 5 (Hyperthreaded):
----------**--------------------------------------------
Physical Processor 6 (Hyperthreaded):
------------**------------------------------------------
Physical Processor 7 (Hyperthreaded):
--------------**----------------------------------------
Physical Processor 8 (Hyperthreaded):
----------------**--------------------------------------
Physical Processor 9 (Hyperthreaded):
------------------**------------------------------------
Physical Processor 10 (Hyperthreaded):
--------------------**----------------------------------
Physical Processor 11 (Hyperthreaded):
----------------------**--------------------------------
Physical Processor 12 (Hyperthreaded):
------------------------**------------------------------
Physical Processor 13 (Hyperthreaded):
--------------------------**----------------------------
Physical Processor 14 (Hyperthreaded):
----------------------------**--------------------------
Physical Processor 15 (Hyperthreaded):
------------------------------**------------------------
Physical Processor 16 (Hyperthreaded):
--------------------------------**----------------------
Physical Processor 17 (Hyperthreaded):
----------------------------------**--------------------
Physical Processor 18 (Hyperthreaded):
------------------------------------**------------------
Physical Processor 19 (Hyperthreaded):
--------------------------------------**----------------
Physical Processor 20 (Hyperthreaded):
----------------------------------------**--------------
Physical Processor 21 (Hyperthreaded):
------------------------------------------**------------
Physical Processor 22 (Hyperthreaded):
--------------------------------------------**----------
Physical Processor 23 (Hyperthreaded):
----------------------------------------------**--------
Physical Processor 24 (Hyperthreaded):
------------------------------------------------**------
Physical Processor 25 (Hyperthreaded):
--------------------------------------------------**----
Physical Processor 26 (Hyperthreaded):
----------------------------------------------------**--
Physical Processor 27 (Hyperthreaded):
------------------------------------------------------**
Logical Processor to Socket Map:
Socket 0:
****************************----------------------------
Socket 1:
----------------------------****************************
Logical Processor to NUMA Node Map:
NUMA Node 0:
****************************----------------------------
NUMA Node 1:
----------------------------****************************
Calculating Cross-NUMA Node Access Cost...
Approximate Cross-NUMA Node Access Cost (relative to fastest):
00 01
00: 1.0 1.1
01: 1.1 1.1
Logical Processor to Cache Map:
Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Unified Cache 1, Level 3, 35 MB, Assoc 20, LineSize 64
****************************----------------------------
Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Instruction Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Unified Cache 5, Level 2, 256 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Instruction Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Unified Cache 6, Level 2, 256 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Instruction Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Unified Cache 7, Level 2, 256 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Instruction Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Unified Cache 8, Level 2, 256 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Data Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Instruction Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Unified Cache 9, Level 2, 256 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Data Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Instruction Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Unified Cache 10, Level 2, 256 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Data Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Instruction Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Unified Cache 11, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Data Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Instruction Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Unified Cache 12, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Data Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Instruction Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Unified Cache 13, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Data Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Instruction Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Unified Cache 14, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Data Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Instruction Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Unified Cache 15, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Unified Cache 16, Level 3, 35 MB, Assoc 20, LineSize 64
----------------------------****************************
Data Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Instruction Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Unified Cache 17, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Data Cache 16, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Instruction Cache 16, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Unified Cache 18, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Data Cache 17, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Instruction Cache 17, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Unified Cache 19, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Data Cache 18, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Instruction Cache 18, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Unified Cache 20, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Data Cache 19, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Instruction Cache 19, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Unified Cache 21, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Data Cache 20, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Instruction Cache 20, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Unified Cache 22, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Data Cache 21, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Instruction Cache 21, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Unified Cache 23, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Data Cache 22, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Instruction Cache 22, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Unified Cache 24, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Data Cache 23, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Instruction Cache 23, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Unified Cache 25, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Data Cache 24, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Instruction Cache 24, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Unified Cache 26, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Data Cache 25, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Instruction Cache 25, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Unified Cache 27, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Data Cache 26, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Instruction Cache 26, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Unified Cache 28, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Data Cache 27, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Instruction Cache 27, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Unified Cache 29, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Logical Processor to Group Map:
Group 0:
****************************----------------------------
Group 1:
----------------------------****************************
这是MsInfo32命令转储(有关服务器的信息):
OS Name Microsoft Windows Server 2012 R2 Standard
Version 6.3.9600 Build 9600
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Name EMTP6
System Manufacturer HP
System Model ProLiant DL360 Gen9
System Type x64-based PC
System SKU 755258-B21
Processor Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
BIOS Version/Date HP P89, 7/11/2014
SMBIOS Version 2.8
Embedded Controller Version 2.02
BIOS Mode UEFI
Platform Role Enterprise Server
Secure Boot State Off
PCR7 Configuration Not Available
Windows Directory ---removed
System Directory ---removed
Boot Device \Device\HarddiskVolume2
Locale United States
Hardware Abstraction Layer Version = "6.3.9600.17196"
User Name Not Available
Time Zone Eastern Standard Time
Installed Physical Memory (RAM) 256 GB
Total Physical Memory 256 GB
Available Physical Memory 246 GB
Total Virtual Memory 294 GB
Available Virtual Memory 283 GB
Page File Space 38.0 GB
Page File ---removed
Hyper-V - VM Monitor Mode Extensions Yes
Hyper-V - Second Level Address Translation Extensions Yes
Hyper-V - Virtualization Enabled in Firmware Yes
Hyper-V - Data Execution Protection Yes
这是TaskManager和我的程序结果的屏幕截图:
或者,如果Windows决定在节点1上启动它:
来自另一个服务器的预期行为:
OS Name Microsoft Windows Server 2008 HPC Edition
Version 6.1.7601 Service Pack 1 Build 7601
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Name COMPUTE-13-6
System Manufacturer HP
System Model ProLiant DL160 G6
System Type x64-based PC
Processor Intel(R) Xeon(R) CPU X5675 @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU X5675 @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
BIOS Version/Date HP O33, 7/1/2013
SMBIOS Version 2.7
Windows Directory C:\Windows
System Directory C:\Windows\system32
Boot Device \Device\HarddiskVolume1
Locale United States
Hardware Abstraction Layer Version = "6.1.7601.17514"
User Name Not Available
Time Zone Eastern Standard Time
Installed Physical Memory (RAM) 48.0 GB
Total Physical Memory 48.0 GB
Available Physical Memory 40.9 GB
Total Virtual Memory 96.0 GB
Available Virtual Memory 88.4 GB
Page File Space 48.0 GB
Page File C:\pagefile.sys
Note: I thought we fixed the problem by changing "Interleaved Memory" parameter in the bios. But i gives us weird results. According to Microsoft Technet we set back the BIOS setting to "NON-Interleaved memory"**(which is required by the OS to see the system as NUMA).
Eri*_*let 12
该错误已由一个新的(尚未发表的)HP Bios(在撰写本文时)修复.
新的Bios(针对HP Proliant DL360和DL380 Gen9)引入了一个新设置:"NUMA Group Size Optimization",可选择[Clustered - default]或[Flat].惠普表示将其设置为持平.
由于服务器的可用性,此答案的场景部分已在DL380而非DL360上进行.但我期望在DL360上有相同的行为.问题消失了,我们只有一个小组.
据我所知,操作系统与BIOS通信以了解CPU配置.Bios在操作系统如何呈现应用程序可用的逻辑处理器(处理器组,亲和力等)方面发挥着重要作用.
关于Microsoft文档支持具有超过64个处理器和处理器组的系统明确指出,只有在逻辑处理器(LC)计数大于64时才会创建多个处理器组.在我们的服务器(56 LC)上,Numa Architecture设置为"Clustered",我们有2个处理器组.在HP Bios开发团队工作的硬件工程师向我解释说,当设置为"Clustered"时,Bios通过将实际数量的逻辑处理器填充到72逻辑处理器(E5 v3系列的最大逻辑处理器数量)来欺骗Windows .我们的DL360中LC的实际数量是56.这就是为什么我们添加2组而不是1的原因.Microsoft文档看起来很准确.我个人认为最好尽可能每个numa节点创建一个组,但在我们的例子中,有一个bug.当HP Bios设置设置为Clustered(默认)时,HP或Microsoft之间很难知道什么是错误的,但Microsoft似乎不支持那个似乎导致我们问题的选项.
在HP Bios for DL360和DL380上,Bios配置"Numa Configuration"设置为"Clustered"(默认)将创建2个组,尽管只有56个逻辑处理器(当超线程时).结果是,对于任何应用程序,一次只能看到一个处理器.可能也是由于惠普通过填充假数量的逻辑处理器来欺骗Windows.听起来微软并不期望这样.我们的C#app无法在2组上运行.在惠普做出他们无法预料的事情时,很难责怪微软.也许有一天,当LC <= 64时,Windows会支持许多组.
关于Prime95.这个CPU压力测试软件在维基百科上有很好的文档,清楚地表明它只会加载到一个处理器组(在Limits部分).
尝试设置代码以构建"优化代码",并将目标平台构建为"x64".(它在我的代码上工作,在80核心的服务器上)
这是我们的MsInfo32:
操作系统名称Microsoft Windows Server 2012 R2 Standard
版本6.3.9600 Build 9600
其他操作系统描述不可用
OS制造商Microsoft Corporation
系统制造商IBM
系统模型系统x3850 X5
系统类型基于x64的PC
系统SKU
处理器Intel(R)Xeon(R)CPU E7- 4870 @ 2.40GHz,2395 Mhz,10 Core(s),20个逻辑处理器
处理器Intel(R)Xeon(R)CPU E7- 4870 @ 2.40GHz,2395 Mhz,10 Core(s),20个逻辑处理器
处理器Intel(R)Xeon(R)CPU E7- 4870 @ 2.40GHz,2395 Mhz,10 Core(s),20个逻辑处理器
处理器Intel(R)Xeon(R)CPU E7- 4870 @ 2.40GHz,2395 Mhz,10 Core(s),20个逻辑处理器
BIOS版本/日期IBM Corp. - [G0E179BUS-1.79] - ,28-07-2013
SMBIOS版本2.7
嵌入式控制器版本255.255
BIOS模式UEFI
BaseBoard制造商IBM
BaseBoard模型不可用
BaseBoard名称基板
平台角色企业服务器
安全启动状态不受支持
PCR7配置不可用
硬件抽象层版本="6.3.9600.17031"
用户名不可用
时区浪漫标准时间
已安装的物理内存(RAM)128 GB
物理内存总量128 GB
可用物理内存53,0 GB
总虚拟内存147 GB
可用虚拟内存67,7 GB
Hyper-V - VM监控模式扩展是的
Hyper-V - 二级地址转换扩展是的
Hyper-V - 在固件中启用虚拟化是
Hyper-V - 数据执行保护是
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