将字节数组连接成一个数组

use*_*669 3 verilog system-verilog

我可以连接这些字节库:

logic [7:0] bank3[0 : 255];
logic [7:0] bank2[0 : 255];
logic [7:0] bank1[0 : 255];
logic [7:0] bank0[0 : 255];
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对某些事情;

logic [32:0] address_array [0:255];
assign address_array = {bank3, bank2, bank1, bank0}; //!This is pseudocode!
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结果数组的大小为256 x 32位.

例:

如果我想读取地址0x0,0x1,0x2,0x3,那么我将访问address_array [0].数组索引的范围应为0到255,宽度为32位.

Mor*_*gan 6

无需使用生成标准for循环将做:

reg [7:0] bank3[0 : 255];
reg [7:0] bank2[0 : 255];
reg [7:0] bank1[0 : 255];
reg [7:0] bank0[0 : 255];
reg [31:0] address_array[0:255];
integer i;

always @* begin
  for (i=0;i<256;i=i+1) begin
    address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]};
  end
end
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在SystemVerilog中:

logic [7:0] bank3[0 : 255];
logic [7:0] bank2[0 : 255];
logic [7:0] bank1[0 : 255];
logic [7:0] bank0[0 : 255];
logic [31:0] address_array[0:255];

always_comb begin
  for (int i=0;i<256;i++) begin
    address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]};
  end
end
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正如格雷格所说,这也可以利用foreach:

always_comb begin
  foreach ( bank_all[i] ) begin
    bank_all[i]= { bank_stack3[i], bank_stack2[i], bank_stack1[i], bank_stack0[i]};
  end
end
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解决方案2

这个问题实际上指出,不是所有的银行都垂直地"堆叠"在一起,而是将bank0重新整形以利用32位宽度.bank0将在到达bank1之前完全读取.

localparam DEPTH = 8;
logic [7:0] bank0[0 : DEPTH-1];
logic [7:0] bank1[0 : DEPTH-1];
logic [7:0] bank2[0 : DEPTH-1];
logic [7:0] bank3[0 : DEPTH-1];

logic [7:0]       bank_stack [(DEPTH*4) -1];
logic [(8*4)-1:0]   bank_all  [0 : DEPTH-1];

always_comb begin
  //First reshape vertically stack banks
  // IEEE 1800-2012 Section 11.4.14 Streaming operators
  {>>{bank_stack}} = {>>{bank0, bank1, bank2, bank3}};

  //Second reshape, flatten to 4 bytes wide.
   foreach ( bank_all[i] ) begin
    bank_all[i]= { bank_stack[i], bank_stack[i+1], bank_stack[i+2], bank_stack[i+3]};
  end
end
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EDA Playground的简短示例.

感谢GregIEEE 1800-2012第11.4.14节流媒体运营商的深入了解.

  • 对于SystemVerilog,你也可以使用foreach-loop而不是for循环`foreach(address_array [i])` (2认同)