makefile 模式规则:单个通配符,先决条件中的多个实例

joh*_*hen 5 design-patterns makefile wildcard

希望这是一个关于 make 模式规则的基本问题:我想在规则的先决条件中多次使用通配符,即在我的 Makefile 中我有

data/%P1.m: $(PROJHOME)/data/%/ISCAN/%P1.RAW
        @echo "  Writing temporary matlab file for $*"
        # do something

data/%P2.m: $(PROJHOME)/data/%/ISCAN/AGP2.RAW
            @echo "  Writing temporary matlab file for $*"
            # do something
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在此示例中,我尝试在通配符 % 为 AG 时调用 make。两个文件 $(PROJHOME)/data/AG/ISCAN/AGP1.RAW 和 $(PROJHOME)/data/AG/ISCAN/AGP2.RAW 都存在。我尝试以下 make 命令并获得此输出:

[jshen@iLab10 gender-diffs]$ make data/AGP1.m
make: *** No rule to make target `data/AGP1.m'.  Stop.

[jshen@iLab10 gender-diffs]$ make data/AGP2.m
Writing temporary matlab file for AG, part 2...

[jshen@iLab10 gender-diffs]$ ls data/AG/ISCAN/AG*
data/AG/ISCAN/AGP1.RAW  data/AG/ISCAN/AGP2.RAW
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如何在第一个 make 规则中实现同一个通配符的多个实例?

joh*_*hen 4

这似乎有效:

.SECONDEXPANSION:    
data/%P1.m: $(PROJHOME)/data/$$*/ISCAN/$$*P1.RAW
            @echo "Writing temporary matlab file for $*, part 1..."
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