VHDL中CASE语句中的多个赋值

Question

我还是VHDL的新手.我需要在CASE语句中为多个信号赋值,如下所示:

CASE input24 IS
WHEN "00" THEN 
                    output0 <= '1' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "01" THEN 
                    output0 <= '0' ;
                    output1 <= '1' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "10" THEN 
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '1' ;
                    output3 <= '0' ;

WHEN "11" THEN 
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '1' ;

在尝试这个之前,我尝试在这样的单行中分配值

WHEN "00" => output0 <= '1', output1 <= '0', output2 <= '0', output3 <= '0' ;

第二个出错了

found '0' definitions of operator "<=", cannot determine exact 
overloaded matching definition for "<="

而第一个语法错误.

我哪里错了？

有没有办法为单个案例为多个信号分配值？

谢谢

Answer 1

当使用CASE语法时WHEN "00" =>,因此没有使用THEN.因此代码是:

CASE input24 IS
  WHEN "00" =>
    output0 <= '1' ;
    output1 <= '0' ;
    output2 <= '0' ;
    output3 <= '0' ;
...

如果input24是std_logic_vector你必须在一个WHEN OTHERS =>处理剩余编码的情况下input24.代码是:

WHEN OTHERS =>
  output0 <= 'X' ;
  output1 <= 'X' ;
  output2 <= 'X' ;
  output3 <= 'X' ;

对于在单个类似中编写赋值,仍然使用;as语句分隔符,因此不在,问题代码中显示,然后只删除空格.代码是:

WHEN "01" => output0 <= '0'; output1 <= '1'; ...

为了在一个语句中分配多个信号,VHDL-2008支持聚合分配,因此如果您使用的是VHDL-2008,则可以编写:

WHEN "10" =>
  (output3, output2, output1, output0) <= std_logic_vector'("0100");

对于VHDL-2003,解决方案可能是创建一个中间output信号 std_logic_vector,然后分配给它.代码可以是:

  ...
  signal output : std_logic_vector(3 downto 0);
begin
  ...
      WHEN "11" =>
        output <= "1000";
  ...
  output0 <= output(0);
  output1 <= output(1);
  output2 <= output(2);
  output3 <= output(3);

如果output使用了,那么case用于设置具有给定数字的位的确切实现input24可以使用:

LIBRARY IEEE;
USE IEEE.NUMERIC_STD.ALL;

ARCHITECTURE syn OF mdl IS

  SIGNAL output : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

  PROCESS (input24) IS
  BEGIN
    output <= (OTHERS => '0');
    output(TO_INTEGER(UNSIGNED(input24))) <= '1';
  END PROCESS;

  output0 <= output(0);
  output1 <= output(1);
  output2 <= output(2);
  output3 <= output(3);

END ARCHITECTURE;

否则,如果output没有使用该信号,那么case仍然可以通过默认赋值将其简化为输出的'0',因此代码如下:

ARCHITECTURE syn OF mdl IS
BEGIN

  PROCESS (input24) IS
  BEGIN
    output0 <= '1' ;
    output1 <= '0' ;
    output2 <= '0' ;
    output3 <= '0' ;
    CASE input24 IS
      WHEN "00" => output0 <= '1' ;
      WHEN "01" => output1 <= '1';
      WHEN "10" => output2 <= '1' ;
      WHEN "11" => output3 <= '1' ;
      WHEN OTHERS => output0 <= 'X'; output1 <= 'X'; output2 <= 'X'; output3 <= 'X';
    END CASE;
  END PROCESS;

END ARCHITECTURE;