Verilog Testbench Clock

Question

我尝试过多种方式,现在我有点绝望了.我试图在我的测试平台上制作这个时钟问题是在模拟中它不起作用或我的模拟似乎冻结了.我知道它必须是时钟.

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
    end
end
initial begin 
    reset = 0; 
    #15 L = 0; R = 0; H = 0;        
    #20 L = 0; R = 0; H = 1;
    #25 L = 0; R = 1; H = 0;
    #30 L = 0; R = 1; H = 1;
    #35 L = 1; R = 0; H = 0;
    #45 L = 1; R = 0; H = 1;
    #50 L = 1; R = 1; H = 0;
    #55 L = 1; R = 1; H = 1;

    reset = 1; 
    #60 L = 0; R = 0; H = 0;        
    #65 L = 0; R = 0; H = 1;
    #70 L = 0; R = 1; H = 0;
    #75 L = 0; R = 1; H = 1;
    #80 L = 1; R = 0; H = 0;
    #85 L = 1; R = 0; H = 1;
    #90 L = 1; R = 1; H = 0;
    #95 L = 1; R = 1; H = 1;
    $stop ; 
 end 

endmodule

Answer 1

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
 end end

尝试在永久循环上方移动clk = 0.不是每10次切换一次时钟,而是每10个单位将时钟重置为0,然后立即切换它.我认为在某些情况下仍然有用,但可能不是你打算做的.

Answer 2

对于时钟简单地使用

parameter PERIOD = 10; //whatever period you want, it will be based on your timescale

always #PERIOD clk=~clk; //now you create your cyclic clock

//==//

更完整：

module testbench;
timeunit 1ns;
timeprecision 100ps;
initial begin
  $display($time, " << Starting the Simulation >>");
    rstn = 1'b0;
    clk = 0;
    #5 rstn = 1'b1;
end

always #PERIOD clk=~clk;


initial
begin
      $dumpfile("your_choice_of_name.vcd");
      $dumpvars;
end

initial
begin
//whatever you come up
end

endmodule