有没有办法从modelsim模拟中将信号值打印到文件中？

Question

我需要获取几个信号的值来检查模拟(仿真在Matlab中).有许多值,我想将它们放在一个文件中,以便我可以在脚本中运行它并避免手动复制值.

有没有办法自动将几个信号的值打印到文本文件中？

(该设计以VHDL实现)

Answer 1

首先作出这样的转换功能std_logic,并std_logic_vector以 string这样的:

function to_bstring(sl : std_logic) return string is
  variable sl_str_v : string(1 to 3);  -- std_logic image with quotes around
begin
  sl_str_v := std_logic'image(sl);
  return "" & sl_str_v(2);  -- "" & character to get string
end function;

function to_bstring(slv : std_logic_vector) return string is
  alias    slv_norm : std_logic_vector(1 to slv'length) is slv;
  variable sl_str_v : string(1 to 1);  -- String of std_logic
  variable res_v    : string(1 to slv'length);
begin
  for idx in slv_norm'range loop
    sl_str_v := to_bstring(slv_norm(idx));
    res_v(idx) := sl_str_v(1);
  end loop;
  return res_v;
end function;

使用逐位格式具有以下优点:任何非01值将以精确std_logic值显示,而不是例如十六进制表示的情况.

然后,使过程从写入字符串std_logic,并 std_logic_vector提交例如,在rising_edge(clk)这样的:

library std;
use std.textio.all;
...
process (clk) is
  variable line_v   : line;
  file     out_file : text open write_mode is "out.txt";
begin
  if rising_edge(clk) then
    write(line_v, to_bstring(rst) & " " & to_bstring(cnt_1) & " " & to_bstring(cnt_3));
    writeline(out_file, line_v);
  end if;
end process;

上面的例子使用rstas std_logic,and cnt_1和cnt_3as std_logic_vector(7 downto 0).然后,"out.txt"中的结果输出为:

1 00000000 00000000
1 00000000 00000000
1 00000000 00000000
0 00000000 00000000
0 00000001 00000011
0 00000010 00000110
0 00000011 00001001
0 00000100 00001100
0 00000101 00001111
0 00000110 00010010