How do I split 16-bit data into 2 8-bit data in VHDL?

Question

How do I split 16-bit data into 2 8-bit data?

 signal part : std_logic_vector (16 downto 0);
 signal part_1    : std_logic_vector (8 downto 0);
 signal part_2   : std_logic_vector (8 downto 0);

Answer 1

在part实际上17比特,由于16 downto 0是一个17位的范围内,并且part_*同样是9位.

如果范围是15 downto 0和7 downto 0,那么您可以使用以下方式进行拆分:

part_1 <= part( 7 downto 0);
part_2 <= part(15 downto 8);

顺便说一句,Martin Fowler/Phil Karlton引述:

计算机科学有两个难点:缓存失效,命名事物和逐个错误.